LVDS to CVBS Bridge Design
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LVDS-to-CVBS Bridge Design Status
Current build status
- Project: BPI R2 Pro LVDS-to-CVBS Bridge
- Board target: 100 x 65 mm, 4-layer, 2 mm rounded rectangle
- Stackup: Standard 4 Layer with inner GND reference plane intent
- Schematic ERC: clean at last electrical review
- PCB placement: completed manually after automated placement service failed
- Routing: not completed; auto-route timed out after a long server-side run and airwires remain
- Manufacturing status: not production-ready until remaining airwires are routed and DRC is clean
Selected architecture
Banana Pi BPI-R2 Pro CN7 LVDS_TX0 → SN65LVDS822 LVDS receiver → ADV7393 RGB-to-CVBS video encoder → 75 ohm CVBS RCA output.
Main ICs and connectors
Table
| Function | Designator | Part | Notes |
|---|---|---|---|
| LVDS receiver | U1 | SN65LVDS822RGZR | 4-lane LVDS, 3.3 V VDD, 3.3 V VDDIO selected |
| Video encoder | U2 | ADV7393BCPZ-REEL | 16-bit RGB input, CVBS output through DAC1 |
| 3.3 V LDO | U3 | AP2112K-3.3TRG1 | 5 V to 3.3 V rail |
| 1.8 V LDO | U4 | RT9193-18GB | 5 V to 1.8 V rail |
| LVDS FPC input | J1 | FPC-05F-40PH20 | 40-pin, 0.5 mm FPC |
| CVBS output | J2 | PJ-3135-Y | Yellow RCA jack |
| Power input | J3 | PJ-037A | 2.1 mm barrel jack |
| I2C header | J4 | TSW-104-07-G-S | 1x4 VIO/SDA/SCL/GND |
Datasheet-grounded support circuitry implemented
SN65LVDS822
- VDD pins connected to 3V3.
- VDDIO pins connected to 3V3 to match ADV7393 VDD_IO.
- EP connected to GND.
- MODE14 tied low for 4-lane 7-bit LVDS mode.
- SWAP tied low for default output pinout and internal LVDS termination.
- SLEW tied low for slower output edges.
- SHTDN# pulled high through R10.
- CLKPOL pulled high through R10 net to select rising-edge-valid CLKOUT mode.
- Decoupling populated: 10 nF local caps per power pin plus 100 nF caps per power node and 10 uF rail bulk.
ADV7393
- VDD and PVDD connected to 1V8.
- VDD_IO and VAA connected to 3V3.
- DGND, PGND, AGND, GND_IO, EP connected to GND.
- RSET = 510 ohm 1% to GND for full-drive DAC mode.
- COMP = 2.2 nF to VAA.
- EXT_LF loop filter implemented as 12 nF at EXT_LF, 170 ohm series, 150 nF to GND.
- RESET has 10 k pull-up to 3V3 and 100 nF to GND.
- ALSB tied low through 10 k for default address.
- SFL tied low through 10 k because subcarrier lock is unused.
- DAC1 used for CVBS, DAC2 and ADC3 marked no-connect.
- CVBS topology: DAC1 node has 75 ohm termination to GND and 75 ohm series resistor to RCA center.
Digital video mapping
Practical 24-bit LVDS to RGB565 truncation mapping used:
Table
| ADV7393 input | Source |
|---|---|
| P0..P4 red | SN65 D3, D4, D5, D6, D7 |
| P5..P10 green | SN65 D10, D11, D12, D13, D14, D23 |
| P11..P15 blue | SN65 D25, D26, D21, D22, D24 |
| CLKIN | SN65 CLKOUT |
| HSYNC | SN65 D18 |
| VSYNC | SN65 D19 |
Unused color LSB/control outputs D0, D1, D2, D8, D9, D15, D16, D17, D20 are marked no-connect.
Layout status
Manual placement was completed after the placement service returned a platform-side model error. Current placement:
- J1 FPC on left edge.
- U1 placed near J1 for short LVDS routes.
- U2 placed to the right of U1 for RGB/CLK bus routing.
- J2 RCA on right edge.
- J3 barrel jack on lower-right edge.
- U3/U4 power section near J3.
- J4 I2C header on top-right edge.
- Four mounting holes placed 5 mm in from board corners.
- Routing congestion report says there is enough space for routing.
Validation status
- Electrical checks: clean at last ERC pass.
- Physical DRC: airwires remain because routing did not complete.
- Auto-route attempt timed out after a long server-side run. No second auto-route was run in this session to avoid burning time without clear benefit.
Known risks and required follow-up
- Routing incomplete: The board is not manufacturing-ready until all airwires are routed and DRC is re-run clean.
- CN7 pinout source file not accessible through project file search in this session: the design uses the pin mapping provided in the prompt and prior notes. Before production, visually cross-check J1 pin mapping against Banana Pi BPI-R2 Pro CN7 page 16.
- Linux/RK3568 timing requirement: ADV7393 does not scale or frame-convert. The RK3568 output must be configured for SD-compatible timing and 27 MHz/13.5 MHz RGB input behavior expected by ADV7393 SD RGB mode.
- LVDS polarity/lane order: If the first bring-up shows no image or swapped colors, verify LVDS P/N polarity, VESA/JEIDA mode, and lane order in software/device-tree and swap if needed.
- JLCPCB assembly: Many parts are Extended class; final procurement should verify current LCSC stock before ordering.
Next recommended action
Route the remaining airwires manually or with a routing pass focused on:
- LVDS differential pairs from J1 to U1 with 100 ohm differential control.
- Pixel CLK and RGB bus U1 to U2 with short, direct routing.
- CVBS analog output kept short and isolated from digital bus.
- Power rails and ground stitching.
- Final DRC + Gerber/BOM/CPL/STEP export only after DRC is clean.
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