Fixing Schematic and Routing Issues

Changing U4 VDD to 3V3...

0:30

Started: Change net of U4 VDD pin to net 3V3 (replacing its previous net)

179 days

Severed U4 VDD net connection

0:44

Started: Sever net connection from U4 VDD pin to its current net

179 days

Updated 1 net

0:05

Disconnected U4:VDD

179 days

Connected U4 VDD to 3V3

0:35

Started: Connect U4 VDD pin to net 3V3

179 days

Changed U4 VSS net to GND

0:44

Started: Change net of U4 VSS pin to net GND (replacing its previous net)

179 days

Changed U4 LED0 net

0:54

Started: Change net of U4 LED0 pin to net LED16_chain (replacing its previous net)

179 days

Terminated USB-C CC nets

0:46

Started: Make net connections to terminate USB-C CC pins: connect J3 CC1→R10→GND, J3 CC2→R11→GND, J4 CC1→R12→GND, and J4 CC2→R13→GND

179 days

Defined 5V_OR net

0:45

Started: Create net connections to define net 5V_OR by connecting U9:OUT, U10:OUT, and Q1:VIN and sever their previous nets

179 days

Bundled J3 VBUS pins locally

0:45

Started: Make net connections to tie J3:VBUS1, J3:VBUS2, J3:VBUS3, J3:VBUS4, D2:VBUS, and U9:IN on a single net

179 days

Bundled J4 VBUS pins

0:39

Started: Bundle J4 VBUS1–4 pins with D3:VBUS and U10:IN on a single net

179 days

Connected ORed outputs on 5V_OR

0:34

Started: Connect U9:OUT, U10:OUT, and Q1:VIN on the 5V_OR net to form the ORed 5 V bus

179 days

Finished routing U4 SDA and SCL

0:40

Started: Execute step 2.4: Finish routing U4 SDA and U4 SCL by connecting U4:SDA to the SDA net and U4:SCL to the SCL net

179 days

Worked

0:14

179 days

Stopped due to a problem. Please try again.

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    Organisational Chocolate Speeder Bike

    Organisational Chocolate Speeder Bike thumbnail
    Simplified Power Distribution Board with Single USB-C Input and Dual 5V Rails

    Properties

    Define keepout regions for nets HB100_IF, SDA, and SCL such that their routing remains clear of plane splits and power/ground transitions. No polygon or split shall cross these net routes as traced between their connections. This applies to L2 (GND) and L3 (power) plane boundaries, with a margin sufficient to avoid splits under all conditions.

    150

    mm

    []

    solid

    Pause for user review of placement and silkscreen before routing.

    0Ω jumpers allowed for unavoidable crossovers

    200

    mm

    []

    Stitch GND between L1 and L2 around connectors J5, J3, and J4

    Discourage unnecessary 0Ω jumpers

    Top side only for easier hand soldering

    ["L3"]

    250

    mm

    5

    mm

    Single-layer top copper only; bottom layer for silkscreen/reference

    graph TD SUBUSB1((USB-C IN 1)) SUBUSB2((USB-C IN 2)) SUBUSB1 -- CC1/CC2 Rd, TVS --> OR1[ORing Controller 1] SUBUSB2 -- CC1/CC2 Rd, TVS --> OR2[ORing Controller 2] OR1 -- 5V --> ORBUS[ORed 5V Bus] OR2 -- 5V --> ORBUS ORBUS --> LSW[5V Load Switch] --> FIVEV[5V Rail] SCREWTERM((12V Screw Terminal)) -- Fuse, PFET Polarity Protection --> TWELVEV[12V Rail] FIVEV -- LED, R --> LED5V[5V Debug LED] TWELVEV -- LED, R --> LED12V[12V Debug LED] MCU3V3[3.3V Rail] -- LED, R --> LED3V3[3.3V Debug LED] FIVEV -- Panel LED #1, R --> PANELLED1[Panel LED1 Header] FIVEV -- Panel LED #2, R --> PANELLED2[Panel LED2 Header] FIVEV -- Panel LED #3, R --> PANELLED3[Panel LED3 Header] LSW -- ON/OFF Button --> CONTROL[User Controls] RESETBTN((Reset Button)) -- MCU Reset --> MCU[Teensy 4.1] classDef source fill:#ffe,stroke:#aaa; class SUBUSB1,SUBUSB2,SCREWTERM,RESETBTN source;

    {"GND":["L2"],"5V":["L3"],"3V3":["L3"],"12V":["L3"],"*":["L1","L4"]}

    ["L3:5V","L3:3V3","L3:12V"]

    All ERC/DRC warnings (decoupling caps, pull-up/pull-down, voltage ratings, power ratings, missing/incorrect net connections, diode direction, airwires, missing footprints) fully resolved. Top-only placement confirmed. All plug-in headers/modules assigned to the top side. Single-layer-friendly topology preserved. Net class layers and via stitching configured for new L2 (GND) and L3 (power) planes. All manual interventions reviewed and verified.

    Pass (no violations)

    Pass (no violations)

    Compliant (star ground implemented with wide returns)

    1

    L1→Top signals, L2→GND plane, L3→5V/3V3/12V power plane, L4→Bottom signals

    Favor inner-layer returns for high-current paths

    ["L2"]

    Diagram
    


  
    
  
  
    
  



























Battery
5A Fuse
LM2596 Buck Converter
5V Rail
12V Rail
Teensy 4.1
I²C PWM Expander
Servos
MOSFET Driver
12V Solenoid
5V Radar Sensor
HB100 Analog Front End
AFE Digital Output
STAR_GND
Board Edge

    Star ground with wide returns

    Compliant (standard 4-layer, top-copper routing, silkscreen bottom)

    Compliant (HB100 AFE and I2C/UART clear of plane splits)

    { "12V": "3A", "5V": "2A", "3V3": "0.5A", "*": "signal" }

    Standard 4 Layer

    5V_LOGIC = 1 A and 5V_SERVO = 2 A

    Stitch GND between L1 and L2 around connectors J3, J4, and J5

    250

    mm

    20

    mm

    ["L2"]

    L1→Top signals, L2→GND plane, L3→5V/3V3/12V power plane, L4→Bottom signals

    []

    Pricing & Availability

    Distributor

    Qty 1

    Arrow

    $19.47–$27.09

    Digi-Key

    $74.25–$77.02

    LCSC

    $44.48–$44.62

    Mouser

    $67.33–$67.77

    TME

    $1.43

    Verical

    $69.05–$88.21

    Controls