Linear Issues Review

Thought for 1 min 51 sec

Done. I focused the local reroute-prep rules on the hotspot cluster using the direct layout/review workflow: inspect with real-time project tools first, then apply targeted layout-rule changes rather than broad guesses

Updated local rules

Table

Area	Change
J2	keep out / min keep out -> 0.15 mm, local trace width -> 0.15 mm, local via size -> 0.45 mm, via hole -> 0.20 mm
U5	keep out / min keep out -> 0.15 mm, local trace width -> 0.20 mm, local via size -> 0.45 mm, via hole -> 0.20 mm
KEY1	keep out / min keep out -> 0.15 mm, local trace width -> 0.15 mm
KEY2	keep out / min keep out -> 0.15 mm, local trace width -> 0.15 mm
KEY3	keep out / min keep out -> 0.15 mm, local trace width -> 0.15 mm
KEY4	keep out / min keep out -> 0.15 mm, local trace width -> 0.15 mm
KEY5	keep out / min keep out -> 0.15 mm, local trace width -> 0.15 mm

Left unchanged

Current review state

The hotspot prep is in place, but the board is still blocked mainly by existing unrouted/conflicting copper:

96 airwires
9 overlapping copper
0 floating copper in the latest check

What this means

J2 now has friendlier local escape-routing rules for the 0.5 mm FFC area.
U5 keeps a slightly wider local trace rule than the buttons.
The button cluster KEY1 to KEY5 is now loosened consistently for future rerouting.

If you want, I can next:

review the exact nets around J2 and U5 that should get priority first
or tighten the backlight-related area around U5 separately from the button signals

Review priority nets

Separate U5 backlight

Check overlap hotspots

Thought for 2 sec

flux

Set J2's minKeepOut to "0.15mm"
Set J2's keepOut to "0.15mm"
Set J2's traceWidth to "0.15mm"
Set J2's size to "0.45mm"
Set J2's holeSize to "0.20mm"
Set U5's minKeepOut to "0.15mm"
Set U5's keepOut to "0.15mm"
Set U5's traceWidth to "0.20mm"
Set U5's size to "0.45mm"
Set U5's holeSize to "0.20mm"
Set KEY1's minKeepOut to "0.15mm"
Set KEY1's keepOut to "0.15mm"
Set KEY1's traceWidth to "0.15mm"
Set KEY5's minKeepOut to "0.15mm"
Set KEY5's keepOut to "0.15mm"
Set KEY5's traceWidth to "0.15mm"
Set KEY3's minKeepOut to "0.15mm"
Set KEY3's keepOut to "0.15mm"
Set KEY3's traceWidth to "0.15mm"
Set KEY4's minKeepOut to "0.15mm"
Set KEY4's keepOut to "0.15mm"
Set KEY4's traceWidth to "0.15mm"

Thought for 4 sec

flux

Set KEY2's minKeepOut to "0.15mm"
Set KEY2's keepOut to "0.15mm"
Set KEY2's traceWidth to "0.15mm"

Files

Schematic

Layout

3D View

Design Notes

Architecture decisions

Use an ESP32-S3 module as the main MCU for Wi-Fi, Bluetooth, native USB, and larger GPIO budget.
Standardize on an ILI9341 TFT in portrait orientation as the default display path unless a superior larger display is later supplied with its datasheet.
Preserve the existing display connector work as provisional only; do not finalize a large-panel mapping unless a verified module pin table is available.
Use USB-C as the main 5 V input with CC pull-down resistors and input protection.
Generate 3.3 V logic power from 5 V using a buck regulator sized for ESP32 plus peripherals.
Generate display/backlight power separately from 5 V using a boost stage for LED backlight supply and a load switch for panel control.
Include USB UART/JTAG access, BOOT/RESET buttons, microSD, audio codec/I2S header, I2C touch, expansion I/O, and three user buttons.

Button assignments

Reuse the five existing tact switches rather than introducing new button hardware.
KEY1 = BOOT.
KEY2 = RESET.
KEY3 = USER1.
KEY4 = USER2.
KEY5 = USER3.
BOOT remains an active-low manual flash-entry input on ESP32-S3 GPIO0.
RESET remains an active-low manual reset input on ESP32-S3 EN.
USER1/USER2/USER3 are reserved as active-low general-purpose UI buttons and should stay on spare GPIOs during future pin cleanup.

Touch display assumptions

Default display path: ILI9341 TFT in portrait orientation.
Target display can still grow larger later, but only if a superior alternate module is supplied with its datasheet and pin table.
Touch technology: capacitive touch controller over I2C, chosen early to align MCU peripheral allocation.
No verified module datasheet is currently attached for the selected TFT implementation, so exact display connector migration must remain provisional until the chosen module is frozen.
Working assumption for schematic completion: J3 pin 1 = GND, pin 6 = 3V3, pin 4 = I2C_SDA, pin 5 = I2C_SCL, pin 2 = TOUCH_INT, pin 3 = TOUCH_RST.
J2 remains a provisional display-area connector artifact from the earlier large-panel concept; pin 40 is used as LCD_BL_PWR and the remaining pins should not drive future layout decisions for the ILI9341 default path unless the connector strategy is deliberately retained.
J2 pins 38 and 39 are currently carrying optional audio breakout signals from the PCM5102A through series resistors. These assignments remain provisional convenience placeholders.

Completed schematic work in this pass

Confirmed USB-C sink wiring, CP2102N USB-UART wiring, touch connector wiring, and the microSD SPI subset.
Added datasheet-backed AP63203 support values by assigning the bootstrap capacitor to 100 nF and the upper feedback resistor to 196 kΩ.
Added missing PCM5102A hardware-mode support wiring: FMT = GND, FLT = GND, DEMP = GND, XSMT = 3V3, SCK = GND, DIN from ESP32-S3 IO47, and LRCK from ESP32-S3 IO21.
Connected the PCM5102A flying capacitor, VNEG capacitor, and LDOO capacitor using existing placed components.
Tied microSD pin 1 to GND and pin 8 to 3V3 using the current connector symbol pin naming.

Remaining cleanup items after this pass

The lower AP63203 feedback resistor still needs to be separated onto its own dedicated resistor part; the existing R10 placeholder was also reused in the audio path and therefore cannot serve both functions simultaneously.
The display connector remains intentionally isolated except for the confirmed backlight output on J2 pin 40 and provisional audio breakout use of J2 pins 38 and 39.
USB-C SBU1 and SBU2 remain intentionally unconnected and should be documented as NC unless a future feature requires them.

Exact external information still required

The exact display panel or display-module manufacturer part number.
The complete 40-pin panel connector pinout table, including all power rails, grounds, RGB data lines, sync/control pins, backlight pins, and any panel reset or standby pins.
Confirmation of whether the touch interface is on a separate 6-pin cable as currently assumed or integrated into the main display cable.
Connector orientation details for both FFCs so pin numbering is not mirrored during layout.

Audit checklist snapshot

Completed and connected: USB-C sink CC resistors, USB-UART bridge to UART0, buck regulator core power path, I2C pull-ups, touch I2C and interrupt/reset wiring, microSD SPI subset, backlight boost output to J2 pin 40.
Partially connected: ESP32 boot/reset support, backlight feedback/compensation loop, buck feedback divider cleanup, audio output breakout cleanup, display connector J2.
Unresolved due to missing module pin table: J2 RGB data bus, pixel clock, HSYNC, VSYNC, DE, panel reset/standby, panel power rails, touch-controller exact connector orientation/pin numbering.
Review findings: many floating pins remain on J2, several optional/unwired pins remain on U4, U3, and spare ESP32 GPIOs; SBU1/SBU2 on USB-C are also floating and should be left NC or documented.

PCB assumptions

Use a 4-layer board for power integrity and display routing margin.
Keep the ESP32-S3 antenna at a board edge with a no-copper keepout in the antenna zone.
The original placed-component aggregate bounds are approximately 85.13 mm x 116.48 mm and define the minimum occupied envelope for resizing.
The next layout pass should use a portrait-oriented board outline sized only modestly above that envelope, with extra margin for connectors and routing rather than the current oversized low-density board.
UI parts must align along the user-facing edge: display area first, then touch connector, BOOT/RESET/USER buttons, and the primary USB connector in a consistent accessible zone.
Power components should stay grouped away from the antenna and display edge, while audio should remain grouped and isolated from the switching power section.

UI cluster relocation audit

Current placed UI-cluster footprint envelope for J2, U5, and KEY1-KEY5 is approximately 66.25 mm x 58.33 mm on the top layer.
Present positions are already spread along the lower half of the board, with J2 at the lower edge and the button cluster split across multiple locations rather than grouped into a tighter user-facing UI zone.
Board density is low at about 16 percent fill, so there is enough area to re-cluster these parts without resizing pressure.
Placement guidance for the next physical move: keep J2 on the accessible edge, place U5 close to J2 to shorten backlight paths, and group KEY1-KEY5 contiguously for BOOT/RESET/USER access.
Execution blocker in this environment: there is no available placement-mutation or autorouter tool exposed here, so I cannot physically move the layout nodes or eliminate the remaining airwires from this session.

Architecture decisions
Button assignments
Touch display assumptions
Completed schematic work in this pass
Remaining cleanup items after this pass
Exact external information still required
Audit checklist snapshot
PCB assumptions
UI cluster relocation audit