ESP32-S3 PLC Architecture Discussion
Worked for 15 mins 44 sec
Completed the final schematic-gate pass and updated Schematic Review Before Layout. D29 is verified, L2 is now a confirmed shielded Sumida inductor, and U8/U9 FAULT is routed to ESP32 GPIO15 with a 10kΩ pull-up; ERC remains clean.
Open items:
- Layout is still not approved: HR911105A symbol-footprint mapping remains Must Fix because the Flux symbol/footprint readout is ambiguous versus the datasheet.
Suggested next steps:
- Replace HR911105A with a clearly numbered MagJack part/footprint, or manually verify its symbol-footprint mapping.
- After that, update the approval table to “Pass” and proceed to PCB placement.
HOW TO DOWNLOAD SCHEMATIC AS PDF OR AS A ALTIUM PROJECT?
Thought for 8 sec
In Flux, use the Export options from the project UI:
- Open your project.
- Click Export / download from the top toolbar or project menu.
- Choose:
- PDF for schematic/documentation output.
- Altium if available in your export list; otherwise export standard manufacturing/interchange formats such as Gerber, ODB++, IPC-2581, BOM, and Pick-and-Place.
If you don’t see an Altium export option, Flux may not support direct Altium project export for this project. For help from Flux support, use: https://docs.flux.ai/Introduction/getting-support.
Export and verify files
Export schematic PDF
Export BOM files
Generate manufacturing files
Create export checklist
Thought for 3 sec
Refine this doc
Ask about this doc
ESP32-S3 Industrial PLC Controller — Digital Input Design Notes
Completed DI channel structure
Each DI channel now includes:
- Pluggable terminal connection on J5.
- 24 V PNP/sourcing-compatible field input.
- Series input current-limiting resistor: 6.8 kΩ, 0.25 W.
- Connector-side single-line TVS/ESD protection: SPHV36-01ETG-C, 36 V working standoff.
- Reverse-polarity protection diode antiparallel with PC817 LED: 1N4148WX-TP class part.
- PC817 optocoupler.
- Field-side green input indication LED with 10 kΩ current-limiting resistor.
- Logic-side 10 kΩ pull-up to +3V3.
- 100 nF logic-side RC/debounce capacitor to GND.
- DI_MCU test point.
- Logic output to ESP32-S3 GPIO.
GPIO allocation
Table
| Channel | ESP32 GPIO | Logic net |
|---|---|---|
| DI1 | GPIO1 | DI1_MCU |
| DI2 | GPIO2 | DI2_MCU |
| DI3 | GPIO4 | DI3_MCU |
| DI4 | GPIO5 | DI4_MCU |
| DI5 | GPIO6 | DI5_MCU |
| DI6 | GPIO7 | DI6_MCU |
| DI7 | GPIO8 | DI7_MCU |
| DI8 | GPIO9 | DI8_MCU |
DI logic is active-low: when the 24 V field input is active, the PC817 transistor pulls the DI_MCU node low.
TVS review
The previously selected SPHV24-01ETG-C was not suitable for 36 V continuous input:
- VRWM = 24 V.
- VBR minimum ≈ 26.7 V.
- Leakage specified at 24 V only.
- Clamp voltage is already specified as 36 V at transient current.
Therefore, at 36 V continuous field input it could leak heavily, enter breakdown, or clamp, depending on device/process/temperature. It has been replaced by SPHV36-01ETG-C, a 36 V working-standoff TVS candidate.
Input-current and resistor-wattage estimate
Assumptions:
- Field input nominal voltage: 24 V.
- Maximum continuous field input considered: 36 V.
- PC817 input LED forward voltage estimate: 1.2 V.
- Series current limit resistor: 6.8 kΩ.
Nominal 24 V:
I = (24 V - 1.2 V) / 6.8 kΩ = 3.35 mAP_R = I² × R = (3.35 mA)² × 6.8 kΩ = 76 mW36 V continuous:
I = (36 V - 1.2 V) / 6.8 kΩ = 5.12 mAP_R = I² × R = (5.12 mA)² × 6.8 kΩ = 178 mWDecision: 0.25 W resistors are electrically adequate. For production/industrial thermal margin, prefer 1206 or 0.5 W if space allows, especially near field connectors or if ambient temperature is high.
PC817 CTR margin review
The PC817X1CSP9F rank found in the datasheet is guaranteed at IF = 5 mA, VCE = 5 V, Ta = 25°C. The exact part did not provide guaranteed CTR at the original 2.28 mA input current.
- At 10 kΩ input resistance, IF was about 2.28 mA at 24 V and 3.48 mA at 36 V. This is below the guaranteed 5 mA CTR test point, so margin across temperature and aging was weak.
- At 6.8 kΩ input resistance, IF is about 3.35 mA at 24 V and 5.12 mA at 36 V. This improves margin and reaches the datasheet CTR test region at the 36 V high end.
Logic pull-up current is only:
3.3 V / 10 kΩ = 0.33 mAEven with CTR reduced by temperature and aging, the 6.8 kΩ input design has materially better margin than the 10 kΩ design. Final production validation should still test the worst-case low-temperature/high-temperature CTR and aged optocoupler behavior.
LED indication current
Each field-side LED uses an independent 10 kΩ resistor. Approximate current at 24 V with a green LED is:
I_LED ≈ (24 V - 2.0 V) / 10 kΩ = 2.2 mAThis is a low-brightness industrial status indication choice with low power dissipation.
Logic-side voltage safety
The PC817 output side is isolated from the 24 V field side. The collector is pulled up only to
+3V3 through a 10 kΩ resistor, and the emitter is tied to logic GND. Therefore, the ESP32-S3 DI GPIO inputs should not exceed 3.3 V in normal operation.Open verification items before production
- Confirm DI input thresholds against any desired IEC 61131-2 Type 1/2/3 digital input class. The present 6.8 kΩ design improves CTR margin but may still require threshold tuning for a formal input class.
- Confirm PC817 CTR margin over temperature and aging using production lots.
- Confirm SPHV36-01ETG-C surge/ESD capability is sufficient for the declared industrial EMC target; use larger SMBJ36A-class TVS parts if higher surge energy is required.
Completed DI channel structure
GPIO allocation
TVS review
Input-current and resistor-wattage estimate
PC817 CTR margin review
LED indication current
Logic-side voltage safety
Open verification items before production
