Head V2 Export Files

DRC blockers: not fabrication-ready — 75 airwires and 2 overlapping-copper errors. Gerber/ODB fab files were not exported.
Export links — 1/2
Export links — 2/2
Create a single downloadable markdown or text file named head-v2-export-links.md containing the DRC blocker summary and every generated download link. Return only the one markdown download link to that file.
Fix blockers then export
Fix DRC blockers
Show overlap locations
Plan routing cleanup
Check export file
D3
U2
J4 17 - U1 IO12
U1 EN - R3 P2
U7 OUT - C9 P1
J1 CC1 - R1 P1
J1 CC2 - R2 P1
R18 P2 - R19 P1
J1 DN1 - J1 DN2
U6 ADJ - R9 P2
J4 6 - U1 IO15
U6 EN - C5 P1
U1 IO2 - J2 PIN_4
J2 Pin_5 - R18 P1
J1 VBUS_B__1 - D1 A
U1 EN - R3 P2
J4 10 - U1 IO5
J4 8 - U1 IO6
U1 3V3 - R3 P1
U1 IO1 - J2 PIN_3
U1 IO1 - J2 PIN_3
J4 6 - U1 IO15
U1 IO1 - J2 PIN_3
U2 EN - C1 P1
U1 IO2 - J2 PIN_4
J3 3 - U1 TXD0
U6 VOUT - C6 P1
U1 3V3 - R3 P1
R16 P2 - LED1 A
U6 VOUT - C6 P1
J4 9 - U1 IO7
U1 IO1 - J2 PIN_3
D1 K - D2 K
U6 EN - C5 P1
J2 PIN_1 - D2 A
J4 9 - U1 IO7
J1 CC1 - R1 P1
U6 EN - C5 P1
J4 8 - U1 IO6
J4 11 - U1 IO4
U1 IO21 - R16 P1
U6 VOUT - C6 P1
J4 20 - U1 IO38
U7 OUT - C9 P1
J1 DP1 - J1 DP2
U6 VOUT - C6 P1
U1 3V3 - R3 P1
U1 3V3 - R3 P1
J4 11 - U1 IO4
U1 3V3 - R3 P1
R18 P2 - R19 P1
U1 3V3 - R3 P1
J4 18 - U1 IO18
U1 EN - R3 P2
U1 3V3 - R3 P1
J1 DP1 - J1 DP2
J1 DP1 - J1 DP2
U1 IO0 - R4 P2
J4 16 - U1 IO10
U1 IO21 - R16 P1
J1 DP1 - J1 DP2
U2 EN - C1 P1
U7 OUT - C9 P1
J4 21 - U1 IO39
U1 IO0 - R4 P2
J4 15 - U1 IO8
R16 P2 - LED1 A
J4 14 - U1 IO9
J1 DN1 - J1 DN2
J4 14 - U1 IO9
J4 15 - U1 IO8
J4 13 - U1 IO11
U6 VOUT - C6 P1
J4 24 - U1 IO16
U1 IO0 - R4 P2
U6 EN - C5 P1
U1 EN - R3 P2
J1 DN1 - J1 DN2
J1 DP1 - J1 DP2
J4 16 - U1 IO10
J4 20 - U1 IO38
J4 24 - U1 IO16
J1 DN1 - J1 DN2
J1 VBUS_B__1 - D1 A
U6 ADJ - R9 P2
R18 P2 - R19 P1
J4 7 - U1 IO13
D1 K - D2 K
J4 17 - U1 IO12
U6 ADJ - R9 P2
J1 VBUS_A__1 - J1 VBUS_B
J1 VBUS_A__1 - J1 VBUS_B
U5 EN - C3 P1
J4 21 - U1 IO39
J1 CC2 - R2 P1
U1 3V3 - R3 P1
J3 4 - U1 RXD0
R18 P2 - R19 P1
J2 Pin_5 - R18 P1
U1 IO2 - J2 PIN_4
J4 7 - U1 IO13
J4 18 - U1 IO18
J4 10 - U1 IO5
D1 K - D2 K
U1 3V3 - R3 P1
J1 DN1 - J1 DN2
U1 3V3 - R3 P1
J4 13 - U1 IO11
U1 IO2 - J2 PIN_4
J4 19 - U1 IO17
D1 K - D2 K
J4 21 - U1 IO39
J4 19 - U1 IO17
J4 20 - U1 IO38
J2 PIN_1 - D2 A
C9
Capacitance
1uF
J1 GND_A__1 - J1 GND_B
U5 GND - C3 P2
U5 GND - C3 P2
C5
Capacitance
1uF
GND
J2 Pin_2 - R19 P2
U5 GND - C3 P2
J4 3 - J4 12
GND
U5 GND - C3 P2
GND
GND
C8
Capacitance
1uF
J1 SHIELD__1 - D3 GND
C22
Capacitance
100nF
J1 SHIELD__1 - D3 GND
J4 3 - J4 12
J1 SHIELD__1 - D3 GND
U1 GND - U3 VSS
J1 SHIELD__1 - D3 GND
C10
Capacitance
1uF
J2 Pin_2 - R19 P2
U1 GND - U3 VSS
GND
J1 GND_B__1 - J1 SHIELD
U5 GND - C3 P2
J1 GND_A__1 - J1 GND_B
C15
Capacitance
10uF
J4 3 - J4 12
C2
Capacitance
1uF
U5 GND - C3 P2
GND
J1 GND_B__1 - J1 SHIELD
LED1 K - J3 1
U5 GND - C3 P2
GND
C6
Capacitance
1uF
U1 GND - U3 VSS
GND
J4 3 - J4 12
J2 Pin_2 - R19 P2
C7
Capacitance
1uF
U5 GND - C3 P2
C1
Capacitance
1uF
U1 GND - U3 VSS
R2
Resistance
5.1kΩ
R14
Resistance
10kΩ
J1
R11
Resistance
6.19kΩ
SW2
R5
Resistance
4.7kΩ
J5
R13
Resistance
10kΩ
D1
J4
R9
Resistance
12.4kΩ
R6
Resistance
4.7kΩ
SW1
R4
Resistance
10kΩ
R18
Resistance
10kΩ
R12
Resistance
10kΩ
R19
Resistance
10kΩ
D2
R10
Resistance
10kΩ
R1
Resistance
5.1kΩ
R3
Resistance
10kΩ
R16
Resistance
1kΩ
LED1
U6
U7
U1
J2

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Head V2 Layout Architecture Review
Date: 2026-07-14
Why this review was done
The current board is electrically organized enough to route, but the mechanical product requirements are now more important than raw routing completion:
  • SHT31, BH1750, and SGP30 need environmental exposure.
  • USB-C, the 5-pin base/JST cable, UART header, and camera FFC all need connector clearance and cable bend room.
  • The ESP32-S3-WROOM antenna must stay at an exposed board edge with keepout.
  • The enclosure face/camera/plugs may force the PCB to sit back from the exterior wall, which can make on-board environmental sensors ineffective unless they are deliberately exposed.
Current layout observations
Current board target: 65 mm x 78 mm, 4-layer.
Approximate current block positions:

Table


ItemRoleCurrent position / issue
U1 ESP32-S3-WROOM-1MCU + WiFi/BLETop edge, antenna overhanging. This is good and should remain a primary constraint.
J4 camera FFCCamera cableRight side near ESP32. Electrically logical, but cable exit direction must match enclosure/camera location.
J1 USB-CService/programming/powerLeft edge. Reasonable, but should be grouped intentionally with other service connectors.
J2 5-pin JSTBase/soil probe interfaceBottom edge. Good access, but not grouped with USB/UART.
J3 UART headerDebug/programmingUpper-left edge. May be better grouped with USB/JST or moved to test pads if not user-accessible.
U3 SHT31Temperature/humidityLower-left area near J2. Needs airflow and heat isolation.
U4 BH1750Light sensorMid/lower-left, but small and not clearly aligned to an optical window.
U8 SGP30Gas/VOC sensorLower-left area, but not in a clean exposed/vented row.
Regulators U2/U5/U6/U7Power railsMixed near left/center. Should stay away from SHT31/SGP30 if possible.
Remaining DRC issues are largely tied to imported footprint artifacts and routing cleanup, not the high-level floorplan itself.
Main architecture conclusion
The board should be reorganized around mechanical exposure zones, not just made smaller.
A neat row of sensors is useful only if that row lines up with an enclosure vent/window. The product likely needs either:
  1. Single PCB with an exposed sensor edge, or
  2. Main PCB plus a small sensor tongue/daughterboard.
The second option may be mechanically better if plugs/camera cables force the main board to sit away from the enclosure face.
Use four clear zones:

Text


Top edge:
  ESP32-S3-WROOM antenna edge / RF keepout

Upper-middle:
  ESP32 body, boot/reset, local decoupling, short camera bus

Service edge, preferably one side or bottom:
  USB-C + 5-pin JST + UART/test access grouped together

Exposed environmental edge/tongue:
  SHT31 | SGP30 | BH1750, aligned to enclosure vent/window
A better rectangular layout would likely be:

Text


┌──────────────────────────────┐
│ ESP32 antenna edge            │
│ ESP32 module                  │
├───────────────┬──────────────┤
│ Power/USB     │ Camera FFC    │
│ support       │ short to ESP32│
├───────────────┴──────────────┤
│ USB-C | UART/test | JST       │  service connector edge
├──────────────────────────────┤
│ SHT31   SGP30   BH1750       │  exposed sensor edge/window
└──────────────────────────────┘
This is not necessarily the smallest outline, but it is much more product-realistic.
If the board cannot sit near the enclosure face, use a protruding sensor tab or small daughterboard:

Text


Main PCB:
  ESP32, power, USB, JST, UART, camera FFC

Sensor tab/daughterboard:
  SHT31, SGP30, BH1750
  aligned to external vent/window/light aperture
This is likely the best product architecture if environmental measurements matter. It avoids sensors being recessed behind connectors, cables, plastic, or dead-air pockets.
Sensor-specific placement guidance
SHT31 temperature/humidity
  • Put at an exposed edge or vent.
  • Keep away from ESP32, regulators, USB power path, and SGP30 heat.
  • Consider thermal isolation slots/cutouts around the sensor zone.
  • Avoid large copper pours thermally connecting it to heat sources.
SGP30 gas/VOC
  • Needs air exchange; avoid sealed cavities.
  • Keep away from adhesives, silicone, conformal coating, and outgassing plastics.
  • Avoid direct condensation/drip path.
  • Do not place immediately adjacent to SHT31 if temperature accuracy is important.
BH1750 light
  • Needs optical exposure, not just airflow.
  • Align to a light window/aperture/light pipe.
  • Avoid shadows from cables, camera FFC, JST cable, enclosure ribs, or board overhangs.
  • It may not belong in the same exact row as gas/humidity sensors unless the enclosure aperture supports both airflow and light.
Connector grouping guidance
Group service connectors where possible:
  • USB-C
  • 5-pin JST base/soil connector
  • UART/debug header or test pads
This reduces enclosure cutouts, cable keepout zones, and mechanical strain. Camera FFC is different: place it based on camera module position and cable bend direction, not just connector grouping.
2-layer feasibility
A 2-layer board is plausible, but not automatically better.
It may work because:
  • ESP32 module handles RF internally.
  • Most signals are I2C/UART/low-speed GPIO.
  • USB is short.
  • Camera bus is parallel but can be kept short if J4 is placed well.
Risks of 2-layer:
  • Bottom ground plane may get cut up by routing.
  • Camera bus and USB return paths can become poor.
  • More EMI/debug risk.
  • Could require larger board area than 4-layer.
  • More manual routing effort.
Recommendation: try a 2-layer feasibility branch only after mechanical floorplan is locked. Use success criteria:
  • Bottom layer remains mostly continuous GND.
  • USB D+/D- are short and have a clean return path.
  • Camera bus is short and grouped near ESP32/J4.
  • Sensor row/tongue remains exposed and thermally isolated.
  • Board does not grow significantly.
If these fail, stay 4-layer.
Size expectations
With better organization:

Table


TargetNotes
65 x 78 mmCurrent compact baseline, but not well organized mechanically.
60 x 72 mmPhysically placeable, but routing became conflict-heavy in current layout. Could work after a real floorplan redesign, not just compaction.
55 x 65 mmPossible on 4-layer with a better block layout, but mechanical connector/sensor exposure will dominate.
50 x 60 mmAggressive; likely needs strong compromises or a sensor tongue/daughterboard.
Do not optimize only for rectangle dimensions. A small tab or irregular outline may produce a better product than the smallest rectangle.
Before mutating placement again, answer these mechanical questions:
  1. Which enclosure face contains the camera opening?
  2. Which face should sense light?
  3. Where will airflow vents be?
  4. Do USB-C and JST need user access, or only assembly/service access?
  5. Does UART need a connector, or can it become test pads?
  6. Which direction should the camera FFC exit/bend?
  7. Can the board have a small sensor tongue/protrusion?
  8. Can sensors be on a daughterboard connected by a short cable/FFC?
Once those are answered, do a fresh block placement before routing:
  1. Lock ESP32 antenna edge.
  2. Lock camera FFC relative to camera/cable direction.
  3. Group USB/JST/UART on service edge.
  4. Create exposed sensor edge/tongue and place sensors there.
  5. Place power/regulators away from SHT31/SGP30.
  6. Place passives.
  7. Route camera and USB first, then power, then low-speed nets.
Do not keep iterating the current scattered layout. Redesign the board floorplan around exposure and connector mechanics. My recommended next layout pass is a fresh floorplan, preferably:
  • ESP32 antenna on top edge.
  • Camera FFC on the edge closest to the camera module.
  • USB/JST/UART grouped on one service edge.
  • Sensors in a clean exposed row or, better, on a small sensor tongue/daughterboard.
  • Keep 4-layer for the next pass; evaluate 2-layer only after this floorplan is mechanically coherent.
  • Why this review was done

  • Current layout observations

  • Main architecture conclusion

  • Recommended floorplan: single-PCB version

  • Recommended floorplan: sensor tongue/daughterboard version

  • Sensor-specific placement guidance

  • SHT31 temperature/humidity

  • SGP30 gas/VOC

  • BH1750 light

  • Connector grouping guidance

  • 2-layer feasibility

  • Size expectations

  • Recommended next action

  • Recommended direction

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Head V2

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