Setting Up Board Layers

0:18

What you should do is treat 0.25 mm as your default trace width, enforce 0.15 mm as the minimum only where you truly need to escape fine-pitch pins, and create a separate wider rule for power nets at 0.5 mm. Flux’s trace-width docs explicitly support adding Trace Width, Trace Width Minimum, and related net/trace rules in the Layout Rules area

Practical setup


RuleValueUse
Default Trace Width0.25 mmNormal signal routing
Default Trace Width Minimum0.15 mmFine-pitch escape only
Power-net Trace Width0.5 mmBattery, charger, regulator outputs, main supply rails
How to think about it
  • 0.25 mm default: good beginner-friendly general signal width.
  • 0.15 mm minimum: not your target everywhere, just the narrowest allowed when routing gets tight around IC pins.
  • 0.5 mm for power: use on rails that actually carry meaningful current, especially battery and regulator paths.
In your current Flux view
Since you see:
  • Layout default rule
  • Trace default rule
I’d do this:
Step 1
Open Trace default rule and set:
  • Trace Width = 0.25 mm
  • Trace Width Minimum = 0.15 mm
That gives you a sane global baseline using the documented trace-width rule flow
Step 2
For power, don’t try to force the whole board’s default trace width to 0.5 mm. Instead, add a more specific rule for power nets. Flux’s layout workflow is rule-driven and supports selector-based / target-specific rule application rather than only one board-wide width
What if you don’t know how to target power nets yet?
Then for now:
  • set the global trace defaults to 0.25 / 0.15 mm
  • remember to manually make important power traces wider later
  • once your nets exist, create a dedicated rule for nets like:
    • VBAT
    • USB_5V
    • regulator outputs
    • main 3V3 rails

Best fit for your EEG board


Net typeRecommended width
Fine-pitch IC escape0.15 mm
Normal digital/control/sensor signals0.25 mm
General power rails0.5 mm
Sensitive EEG analog inputsKeep short first; width is less important than shielding/return path
My recommendation
Set this now:
  • Trace default width = 0.25 mm
  • Trace default minimum = 0.15 mm
Then later add:
  • Power-net trace width = 0.5 mm
If you want, I can help you write the exact next rule for power once you tell me what options appear when you click Add under rules.
32 days
How do I create multiple schematic sheets in this project and connect them with ports?
32 days

0:27

Reading docs about How do I create multiple schematic sheets in Flux and connect them using ports or net portals between sheets?.

Reading docs about How do net portals work in Flux for connecting signals across modules or multiple schematic sheets?.

Gathering compliance guidance.

This is the most relevant entry I found related to the topic:
Does Flux support multi-sheet schematics or reusable sub-circuits?
Flux uses a single-sheet schematic approach. However, you can section your schematic or create Modules—reusable sub-circuits that encapsulate part of your design.
How can I label nets or create named connections in the schematic?
Use net portals by placing a portal symbol on a wire and entering the desired net name. Any portal sharing that name will automatically connect the nets. Learn more in the Schematic – Net Portals guide.
Show module docs
Net portals steps
Module vs portals
32 days

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    FlowState Headband EVT1 thumbnail
    FlowState Headband EVT1 — 4-Channel EEG Calibration Device
    Closed-loop EEG neurofeedback headband for theta/beta baseline calibration. 4-layer mixed-signal PCB, 40x30mm.
    Core ICs:
    • ADS1299-4PAG (TI) — 4-channel 24-bit EEG analog front end, SPI interface, 250 SPS
    • nRF5340 (Nordic) — Dual-core BLE 5.3 SoC, 128 MHz app core + 64 MHz network core
    Key requirements:
    • Separate analog and digital power domains (dual LDO: LP5907 for AVDD, AP2112 for DVDD)
    • Split analog/digital ground planes with single-point connection
    • 6 electrode inputs (4 active + 1 reference + 1 DRL) with individual TVS ESD protection on each
    • LIS2DH12 accelerometer (I2C) for motion artifact detection
    • MCP73831 USB-C battery charging (300-500 mAh LiPo)
    • 2.4 GHz chip antenna or PCB trace antenna at board edge with 10mm keepout
    • Conformal coating for sweat/moisture protection
    Reference designs:
    • Analog front-end: TI ADS1299 EVM (SBAS499)
    • Digital/BLE: Nordic nRF5340 DK reference schematic
    Critical constraint: Microvolt-level EEG signals — analog input routing and power supply filtering are the highest-priority layout
    concerns.

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