Manufacturing Readiness Checklist
1:39
Analyzing the schematic.
Analyzing the PCB layout.
Running design review.
Reviewing the bill of materials.
Checking.
Evalu.
Here’s a manufacturing-readiness pass on your design, starting with the BOM and then walking through the rest of the checklist.
1) BOM review
BOM summary
- Good news: most populated parts have valid MPNs and current source coverage.
- Main blockers are:
Critical sourcing blockers
| Item | Issue | Why it matters | Recommended action |
|---|---|---|---|
| U2 | Obsolete, stock effectively unavailable | Manufacturing risk / redesign risk | Replace with a currently active LDO |
| Y1 | 0 stock in review | Immediate procurement blocker | Replace or pre-approve alternate |
| C2 | Generic part, MPN=OPT | Not manufacturable as-is | Assign a real manufacturer + MPN |
| J4 | No MPN | Assembly house cannot source deterministically | Assign exact header part |
| J5 | No MPN | Same as above | Assign exact header part |
Lower-priority BOM concerns
| Item | Issue | Note |
|---|---|---|
| J2 | Review says no MPN, schematic shows part name only | Likely property mismatch; verify BOM field mapping |
| MCU_TXD, MCU_RXD, MCU_BOOT | No stock data | Usually acceptable if these are custom/test pads, but confirm fab footprint is standard |
| IC1 | Manufacturer shown as TI in BOM context, but project constraint says Espressif ESP32-C3 family | Fix metadata so purchasing docs are clean |
Cost optimization opportunities
| Opportunity | Observation | Likely impact |
|---|---|---|
| Standard passives already consolidated | R1, R3, R5 share one MPN; R2, R4 share one MPN; many capacitors are already grouped | Good |
| Review 0805 capacitor mix | C1, C17, C21, C22, C30, C19 are intended as one family, but C19 shows 12 uF while the same MPN elsewhere shows 10 uF | Clean up property inconsistency before release |
| Mouser-only dependence on some 1 uF parts | many of the C3/C5/C7-family entries show practical stock mainly at Mouser in review | Consider second-source if volume matters |
| RF / specialty parts | Y2, L4, L1 are more specialized | Keep alternates approved if production scale increases |
- Replace obsolete U2
- Replace unavailable Y1
- Convert C2 from generic to real MPN
- Add real MPNs to J4 and J5
- Verify BOM property mapping on J2
- Resolve inconsistent capacitance metadata on C19
- Correct manufacturer metadata on IC1
2) Design rule / connectivity review Current DRC/ERC status
- 53 airwire errors
- 6 single-pin nets
- No missing-footprint errors
- No undriven-net errors in the fetched review set
Single-pin nets
| Net | Finding | Likely meaning |
|---|---|---|
Net 28 | U1 XOUT only | Unused oscillator pin or incomplete crystal connection |
Net 37 | U1 XIN only | Same concern |
Net 34 | J1 CMD only | SD interface incomplete / intentionally unused but not marked NC |
Net 30 | J1 DAT2 only | Same |
Net 36 | J1 CD only | Card-detect left floating or unused |
Net 7 | Y2 pin 2 only | Antenna second pad likely intentionally floating depending on footprint, but verify against datasheet/land pattern intent |
- The board is not layout-ready yet because of the large airwire count.
- The single-pin nets need to be explicitly resolved:
- If intentional, mark or document them properly.
- If accidental, finish the schematic/net definitions before fab release.
- Close all airwires before generating fabrication outputs.
- Verify whether U1 crystal-related pins are intentionally unused.
- Verify whether unused pins on J1 should be NC or connected.
- Verify whether Y2 pad 2 is intentionally unconnected per its recommended layout.
3) Passive consolidation opportunities
Already well consolidated
- Replace placeholder C2 with a real stocked MPN and see whether it can share a family already used elsewhere.
- Normalize C19 metadata to match the rest of its MPN group if it is truly the same part.
- Consider whether C27 and C29 can share the same approved AVL as other bulk input caps in your purchasing flow.
- Passive consolidation is mostly good already.
- Biggest win is not part-count reduction, but cleanup of placeholder/inconsistent metadata.
4) Footprint / package verification for assembly What looks good
- Review reports no missing footprints.
- The following critical parts have assigned footprints/models in layout:
Items needing manual verification before release
| Item | Concern | Check |
|---|---|---|
| C2 | Generic placeholder with 0603 package only | Confirm the intended footprint and source part exactly match |
| IC1 | Part naming/metadata inconsistency | Confirm exact ESP32-C3 package and land pattern |
| U2 | Footprint exists, but part is obsolete anyway | Re-verify footprint after replacement |
| J4, J5 | Generic headers | Confirm the exact hole size, pitch, and assembly style required |
| J1 | Placed on inverted side | Confirm assembly side and stencil expectations |
| Y2 | RF antenna footprint is sensitive | Verify keepout/orientation against vendor land pattern |
| Y1 | Needs replacement due to availability | Recheck pad geometry if alternate selected |
- No missing footprints
- But footprint verification is not complete until placeholder and generic parts are replaced with final production MPNs.
5) Board bring-up test plan Bring-up goals
- Confirm no shorts
- Verify power rails
- Confirm boot/debug access
- Confirm MCU operation
- Confirm ADC/load-cell path
- Confirm storage and GPIO interfaces
- Visual inspection under microscope
- Check polarity/orientation for ICs, connectors, and polarized placement assumptions
- Measure resistance from each power rail to GND with power off
- Confirm no solder bridging on fine-pitch devices:
- Power from current-limited bench supply through J2
- Start with low current limit
- Check rails in order:
PP12V0PP5V0PP3V3
- Verify regulator outputs and ripple with oscilloscope
- Use MCU_TXD, MCU_RXD, and MCU_BOOT
- Confirm boot mode entry
- Confirm serial download / flashing
- Run minimal firmware:
- heartbeat GPIO
- UART banner
- ADC interrupt visibility
- Verify I2C pull-ups and bus activity on:
- Confirm U1 responds over I2C
- Check
INT_ADC_DRDYinterrupt behavior - Validate load-cell input path through J3
- Validate switch/header interface on J4 and J5
- Validate MicroSD interface on J1 if intended for first spin
- Zero-scale reading
- Known weight calibration
- Noise floor measurement
- Repeatability test
- Long-duration drift test
- Brownout / power-cycle test
Bring-up checklist table
| Test | Pass criterion |
|---|---|
| Visual inspection | No tombstones, bridges, missing parts |
| Rail shorts | No low-ohmic short to GND on primary rails |
| 12 V input | Stable at connector input |
| 5 V rail | Present and within tolerance |
| 3.3 V rail | Present and within tolerance |
| MCU boot | Device enters boot/program mode |
| UART | Boot logs / firmware banner visible |
| I2C | ACK from ADC |
| ADC DRDY | Interrupt toggles as expected |
| Load-cell input | Stable raw readings with no load |
| Calibration | Known-mass reading within target error |
| Reboot behavior | Clean restart across repeated cycles |
Overall manufacturing readiness verdict Status
- Not ready for fabrication release yet
Find U2 replacement
Find crystal replacement
Check remaining DRC
56 days
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