Schematic Component Count

flux

0:00

Work done
  • Re-ran the Floating Pin ERC check and confirmed there are currently 0 Floating Pin warnings.
  • Checked specifically for U_BLE Floating Pin findings; the current ERC report contains no U_BLE floating-pin entries.
  • No schematic nets, designators, components, or connections were modified in this pass because the current authoritative ERC report is already clean.
Success criteria review
  • ✅ Floating Pin warning count is 0.
  • ✅ No wired nets, designators, or other components were modified.
  • ✅ Current ERC confirms no remaining U_BLE floating-pin warnings.
Next steps
  • The schematic is ready for PCB-layout handoff. I can next help with board sizing, stackup, and placement constraints for layout.
3 days

flux

0:03

Work done
  • Re-ran the Floating Pin ERC review for U_BLE and for the full schematic.
  • The current Floating Pin ERC report now shows 0 floating-pin checks, so there are no remaining U_BLE floating pins to mark.
  • No wired nets, designators, or other components were modified.
Success criteria review
  • ✅ Floating Pin warning count is 0.
  • ✅ No non-U_BLE floating-pin warnings are present.
  • ✅ No net, designator, or component changes were made during this verification pass.
Next steps
  • The schematic is ready for PCB-layout handoff. I can next help with board sizing, stackup, and component placement.
Full design review
Place components
Check BOM completeness
Export manufacturing files
3 days
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Implementation Plan Update - Power Sequencing Requirements
Project: BarbellAI Puck V1 Radar Core
Scope: Requirements capture and cleanup alignment only. No PCB or layout work in this update.
Objective
Capture the authoritative three-rail power network and startup/reset sequencing constraints for the radar core, aligned to the Barbell Hardware Reference MCP and SWRS237C section 7.11.3 rail ownership.
Authoritative Rail Ownership
  • 1P8_ANA first from U2 at 1.8 V feeding only the analog/clock/baseband/VCO groups on IC1:
    • VIOIN_18
    • VIN_18CLK
    • VIOIN_18DIFF
    • VIN_18BB
    • VIN_18VCO
  • 1P2_CORE second from U1 at 1.2 V feeding only:
    • VDDIN
    • VIN_SRAM
    • VNWA
  • 1P3_RF third from U5 at 1.3 V feeding only:
    • VIN_13RF1
    • VIN_13RF2
Startup Sequence Requirement
Record the required enable and power-good ordering as:
  1. 1P8_ANA first
  2. 1P2_CORE second
  3. 1P3_RF third
System Reset Gating Requirement
  • SYS_RESET_N must remain asserted low until all three rails are stable.
  • Reset release must depend on successful completion of the full rail bring-up sequence using power-good status.
U5 Hold Requirement
  • Hold any U5 substitution edits pending exact Flux library availability of TPS7A2013PDBVR.
  • Do not substitute to alternate package variants during this hold state.
Result
This document now reflects the cleaned-up rail naming and sequencing baseline for the BarbellAI Puck V1 Radar Core schematic and explicitly excludes any PCB/layout phase work.

    Objective

    Authoritative Rail Ownership

    Startup Sequence Requirement

    System Reset Gating Requirement

    U5 Hold Requirement

    Result

Documents

    Implementation Plan Update - Power Sequencing Requirements

    Design Notes

    Project Specification

    design-notes-routing-audit

    BLE Subsystem Pin Mapping

    USB-C Charger Subsystem Pin Mapping

    Priority 3 Battery Connector and Switch Cleanup

    Priority 4 Battery Monitor and Priority 5 RGB LED Pin Mapping

Assets

No assets added.

BarbellAI Puck V1 Radar Core

BarbellAI Puck V1 Radar Core thumbnail
Low-noise 1.3V buck regulator for the 1P3_RF rail, 3A output, VBATT input, QFN RPU 10-pin 2.0x2.0mm

Properties

Three regulated rails required: 1.8V first, 1.3V VDD_CORE second via TPS62810-class buck, 1.2V RF third. Authoritative 1P3_RF implementation: U6 TPS62913RPUR low-noise buck drives 1P3_RF directly from VBATT. U5 is retired. Sequencing must follow 1.8V -> 1.3V -> 1.2V with power-good gating. SYS_RESET_N must remain low until all three rails are stable.

U

Texas Instruments

Do not regress to the retired U5/TPS7A2013PDBVR LDO plan unless explicitly requested. Authoritative implementation uses U6 TPS62913RPUR for 1P3_RF.

Authoritative MCP rail mapping: U1 TPS62810QWRWYRQ1 -> 1P2_CORE only for IC1 VDDIN/VIN_SRAM/VNWA; U6 TPS62913RPUR low-noise buck -> 1P3_RF directly from VBATT; U2 TPS7A8400RGRT configured to 1.8V -> 1P8_ANA only for IC1 VIOIN_18/VIN_18CLK/VIOIN_18DIFF/VIN_18BB/VIN_18VCO. U5 is retired. Any earlier references to U5 as an LDO or to TPS7A2013PDBVR are superseded and must not be reinstated unless explicitly requested.

Low-noise buck

QFN RPU 10-pin 2.0x2.0mm

TPS62913RPUR

Pricing & Availability

Distributor

Qty 1

Arrow

$40.67–$41.76

Digi-Key

$9.80–$10.13

HQonline

$1.11–$1.14

LCSC

$56.32

Mouser

$64.29

TME

$10.90

Verical

$2.13–$48.46

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