Schematic Component Count
12:58
Exploring auto layout for PCB.
Analyzing the schematic.
Analyzing the PCB layout.
Looking for "antenna keepout area module placement edge overhang distance PCB antenna Raytac MDBT50Q-1MV2 layout guidelines" in index.php?index_id=43
Placing components.
Considering PCB placement.
Gathering information.
Considering layer adjustments.
Evaluating J2 and U1 positions.
Inspecting D_TVS adjustments.
Considering D_TVS positioning.
Considering layout adjustments.
Resolving tight issues.
Evaluating connections and adjustments.
Calculating dimensions and avoiding errors.
Evaluating spatial constraints.
Analyzing keepouts and adjustments.
Exploring layer configurations.
Clarifying constraints.
Running design review.
Auto-layout is complete. The components were rearranged with no overlap or out-of-bounds placement issues; the remaining layout errors are unrouted airwires, so the next step is routing.
Check remaining airwires
Manual routing help
Find dense areas
Set layout rules
3 days
Placed components
11:30
Placed 35 component(s): U1, C7, C8, R_BV1, CL1, C13, C2, R_VBUS_LINK, R5, R_PROG, R_LR, C11, R_LG, C1, C9, D_REV, J_POGO_GND, J_BAT, C10, J_POGO, C_POGO_IN, R_LB, C12, R6, C14, C6, D_POGO_TVS, C3, J2, F_POGO, D_LED, CL2, C4, U2, R_BV2
3 days
Refine this doc
Ask about this doc
Design Notes
BarbellAI Clip V1 locked MCU revision
- Preserved the existing USB-C connector, USB-C sink/protection path, protected 5 V rail, and 3.3 V regulator.
- Replaced the stale ESP32-S3 module with U1 = Raytac MDBT50Q-1MV2 based on Nordic nRF52840.
- The existing 3.3 V regulator remains valid for the module because MDBT50Q-1MV2 supports a supply range compatible with the regulated 3.3 V rail used by this design.
- The Raytac module uses an integrated chip antenna and requires a no-ground keepout under the antenna on all layers. Placement intent remains board-edge placement with at least 5 mm antenna keepout per the module mechanical guidance.
- Removed obsolete ESP32-S3 boot/strapping assumptions from the design record. GPIO0, GPIO45, and GPIO46 notes no longer apply.
SWD programming interface
- Added J2 = TC2030-IDC-NL as the preferred compact Tag-Connect programming/debug header.
- Corrected J2 to the standard Cortex-M Tag-Connect mapping:
- Pin 1 = VTref / 3.3 V
- Pin 2 = SWDIO
- Pin 3 = RESET
- Pin 4 = SWDCLK
- Pin 5 = GND
- Pin 6 = NC
ICM-42688-P integration
- U2 = ICM-42688-P remains the IMU in LGA-14 package.
- Powering both VDD and VDDIO from the 3.3 V rail.
- Updated local IMU decoupling to match the datasheet application circuit:
- C12 = 0.1 uF X7R on VDD, placed as close as possible to U2 pin 8 VDD
- C14 = 2.2 uF X7R on VDD, adjacent to C12 on the same VDD rail
- C13 = 10 nF X7R on VDDIO, placed as close as possible to U2 pin 5 VDDIO
- Removed the prior 10 uF local IMU bulk capacitor.
- Wired SPI in 4-wire mode to the nRF52840 using non-NFC GPIOs:
- P0.14 -> IMU_SCLK -> U2 pin 13 AP_SCL/AP_SCLK
- P0.13 -> IMU_MOSI -> U2 pin 14 AP_SDA/AP_SDIO/AP_SDI
- P0.16 -> IMU_MISO -> U2 pin 1 AP_SDO/AP_AD0
- P0.15 -> IMU_CS -> U2 pin 12 AP_CS
- P0.17 -> IMU_INT1 -> U2 pin 4 INT1/INT
- P0.09 and P0.10 are not used by the IMU interface.
- Datasheet pin handling:
- Pin 7 RESV tied to GND
- Pins 2, 3, 10, and 11 marked NC per datasheet allowance
- Pin 9 INT2/FSYNC/CLKIN tied to GND because FSYNC and CLKIN are unused in this design
- Firmware note: INT2 must be disabled in firmware because pin 9 is grounded
- Placement intent:
- U2 must remain on rigid portion near clamp centerline
- Orient U2 so X/Y/Z axes align with barbell sleeve reference frame
External low-frequency crystal
- Added the required external 32.768 kHz LFXO network for U1 because MDBT50Q-1MV2 does not integrate the low-frequency crystal.
- Y1 = ABS07-32.768KHZ-T on nets XL1 and XL2.
- XL1 connects U1 P0.00/XL1, Y1 pin 1, and CL1 pad 1.
- XL2 connects U1 P0.01/XL2, Y1 pin 2, and CL2 pad 1.
- CL1 and CL2 both return to GND.
- Initial crystal load capacitors are 12 pF each as a first-pass value to be tuned against crystal CL and board stray capacitance if needed.
Review intent for next pass
- Verify no stale ESP32-specific notes remain in project data.
- Verify SWD header pin numbering against the exact Tag-Connect footprint convention before PCB release.
- Verify the Raytac antenna keepout is preserved in layout placement and copper rules.
External 32.768 kHz LFXO addition
- U1 requires an external 32.768 kHz crystal on XL1 and XL2 for the intended low-power BLE operating mode.
- Y1 = ABS07-32.768KHZ-T was selected as the LFXO crystal.
- XL1 net connects U1 P0.00/XL1 to Y1 pin 1 and CL1.
- XL2 net connects U1 P0.01/XL2 to Y1 pin 2 and CL2.
- CL1 and CL2 are both 12 pF load capacitors to GND as the initial implementation, subject to tuning if measured stray capacitance requires adjustment.
C1 correction
- C1 is a 100 nF decoupling capacitor from 3V3 to GND in the current clip schematic.
- The prior all-GND short condition on C1 was corrected so C1 pin 1 is now on 3V3 and C1 pin 2 remains on GND.
Clip-power and LFXO canonical verification
- Verified U2 clip-power wiring against the authoritative ICM-42688-P pin map used in this project:
- U2 pin 8 = VDD on 3V3
- U2 pin 5 = VDDIO on 3V3
- U2 pin 6 = GND
- U2 pin 7 = GND
- Verified C1 now bypasses 3V3 to GND and is electrically on the same 3V3 rail serving U2 pin 8 VDD and pin 5 VDDIO.
- Verified the external 32.768 kHz LFXO network matches the canonical clip-lfxo intent:
- XL1 connects U1 P0.00/XL1, Y1 pin 1, and CL1 pin 1
- XL2 connects U1 P0.01/XL2, Y1 pin 2, and CL2 pin 1
- CL1 pin 2 and CL2 pin 2 both connect to GND
- Post-fix ERC remains clean for the modified power and crystal nets with no shorted-component, missing-power, single-pin-net, or undriven-net warnings introduced by this corrective pass.
Clip V1 schematic lock - 2026-04-22
- MCU: U1 = Raytac MDBT50Q-1MV2 (nRF52840); external 32.768 kHz LFXO block verified canonical (Y1 + CL1 + CL2, both load-cap returns to GND).
- IMU: U2 = ICM-42688-P on 3V3; C_VDD = 100 nF on pin 8 VDD and C13 = 100 nF on pin 5 VDDIO per Invensense DS-000347 decoupling guidance; pin 9 = GND (INT2/FSYNC/CLKIN tied to GND, unused); pins 2/3/10/11 = NC per datasheet.
- Power: C1 rewired as true 3V3-to-GND bypass cap (Shorted Components review = Success); 3V3 rail = AP2112K-class 3.3 V regulator output; USB-C protected entry upstream.
- SWD: Tag-Connect TC2030-IDC-NL header J2 to U1 (3V3, SWDIO, nRESET on P0.18, SWDCLK, GND).
- SPI (MCU↔IMU): IMU_CS=P0.15/pin12, IMU_SCLK=P0.14/pin13, IMU_MOSI=P0.13/pin14, IMU_MISO=P0.16/pin1, IMU_INT1=P0.17/pin4.
- ERC state at schematic lock: 0 pin-to-pin / 0 missing-power / 0 single-pin / 0 undriven-net / 0 shorted-component; floating-pin count = 38 (all intentional-unused nRF52840 GPIOs on U1, see note below).
- Known remaining ERC warnings: 38 floating-pin warnings on U1 are intentional-unused GPIOs; per design policy we DO NOT add NC instance symbols on the schematic; correct closure is to set pin type = NoConnect on unused pins inside the MDBT50Q-1MV2 library part, which is tracked in the V1 manual-Flux-library-editor backlog alongside the puck IWR6843 pin-type pass.
Welcome 👋
Flux helps you build PCBs faster with an AI teammate!
Create your account to collaborate, stay updated, fork your own version, and get instant answers from our AI agent.