Motion Controller Design


Thought for 11 mins 49 sec
2/4 USB-Differenzialpfad kontrolliert routen und prüfen

Routing-Preflight und Regelprüfung durchführen

USB-Differenzialpfad kontrolliert routen und prüfen

Power-Pfade und Buck-Boost-Schleifen routen

DRC, Impedanz und Rückstrompfade abschließend prüfen

Thought for 13 sec
Thought for 7 sec
Awaiting 1 background task
Received notification from "USB Routing Check" that it finished — picking the work back up.
Bisher abgeschlossen:
  • Routing-Preflight bereinigt: fehlerhafte U4-Pads 11–15 deaktiviert und Neckdowns für REG_L1/L2 sowie U5-VDD definiert.
  • Router-Preflight anschließend sauber: 0 Anomalien.
  • USB-Routing-Executor ist abgeschlossen, konnte aber wegen fehlender ACUs nicht mehr unabhängig gegen Layout, DRC, Impedanz und Rückstrompfade verifiziert werden.
  • Für den fehlerhaften TPS63001DRCR-Bibliotheks-Footprint wurde ein internes Qualitäts-Ticket eingereicht.
Noch offen
  • USB-Routingbericht und tatsächliche Kupfergeometrie rücklesen
  • USB-Längenabgleich, Viazahl, 90‑Ω-Geometrie und Rückstrompfad verifizieren
  • Power-Pfade VBUS, BAT, SYS, 3V3 und REG_L1/L2 routen
  • Abschließende DRC-, Plane-Coverage- und Rückstromprüfung
Die weitere Ausführung ist aktuell blockiert, weil keine ACUs verfügbar sind.
USB-Bericht prüfen
USB-Routing verifizieren
Offene Punkte dokumentieren

Schematic Design Report
Completion
Completed: all required schematic blocks, named nets, footprints and production MPNs are assigned. The BOM now includes verified manufacturer and manufacturer-part-number properties for all 26 generic resistors and all 14 generic capacitors; manufacturing, passive-rating and ERC checks are clean.
Key Decisions
  • ESP32-S3-WROOM-1-N8R2 selected for certified RF module, PCB antenna, native USB, flash and PSRAM.
  • IIM-42652 selected for low-noise 6-axis SPI motion sensing without magnetometer.
  • BQ24074 provides true dynamic power path; 500 mA USB input mode and 403 mA programmed charge current suit an 800–1000 mAh protected LiPo.
  • TPS63001 buck-boost selected instead of an LDO because a depleted 1S cell cannot maintain regulated 3.3 V through an LDO. Worst-case peak input estimate is 647 mA at 3.0 V, 500 mA output and 85% efficiency.
  • MAX17048 provides low-power ModelGauge SOC without a shunt resistor.
Verification Evidence
  • Schematic contains 76 components and 48 nets.
  • Review returned 0 open Manufacturer Part Number findings, 0 capacitor-voltage findings, 0 resistor-power findings and 0 open findings across all ERC categories.
  • All exposed IC power/ground pins and thermal pads are connected; unused MCU and connector pins are explicit no-connects.
  • USB native pins are GPIO19/20 with 22 Ω series resistors, CC1/CC2 each 5.1 kΩ, data ESD and VBUS fuse/TVS.
Production Passive MPN Groups
  • YAGEO RC thick-film resistors: RC0402FR-075K1L, RC0402FR-0722RL, RC0402FR-072K21L, RC0402FR-072K94L, RC0402FR-0746K4L, RC0402FR-073K01L, RC0402FR-07100KL, RC0402FR-07100RL, RC0402FR-0710KL, RC0402FR-074K7L, plus 0603 LED resistors RC0603JR-071K8L and RC0603JR-071K3L. Ratings are 63 mW for 0402 and 100 mW for 0603, with the selected RC series rated from -55 °C to +155 °C.
  • Murata X7R MLCCs: GRM21BR71C475MA73L (4.7 µF, 16 V, 0805), GRM31CR70J226KE19L (22 µF, 6.3 V, 1206), GRM155R71C104KA88D (100 nF, 16 V, 0402), GRM188R71A105KA61D (1 µF, 10 V, 0603), GRM188R71A225KE15D (2.2 µF, 10 V, 0603), and GRM155R71C103KA01D (10 nF, 16 V, 0402).
  • Samsung X7R MLCC: CL21B106KPQNFNE (10 µF, 10 V, 0805) for TPS63001 input/output capacitance.
  • DC-bias margin: C1–C3 were upgraded to 16 V parts; C4–C6 use 10 V X7R parts, with C5/C6 retained in parallel at the regulator output; C8 remains a physically larger 1206 22 µF/6.3 V part at 3.3 V. These choices provide substantially better effective-capacitance margin than minimum-voltage small-case alternatives.
No passive/MPN warnings remain to justify.
Remaining Risks
  1. The stated 102 mA typical load does not meet 12 h on 800–1000 mAh; firmware must reduce average current to about 60–75 mA or battery capacity must increase.
  2. BQ24074 is a linear charger; at low battery voltage its thermal loop may reduce the programmed 400 mA unless the exposed pad has generous copper and vias.
  3. TH1 is board-mounted. It must be thermally coupled to the cell pouch; otherwise use a pack with a dedicated NTC contact in the next mechanical revision.
  4. USB D+/D− test pads can degrade signal integrity if stubbed; implement as tiny in-line or zero-stub probe pads.
  5. Final USB impedance and antenna keepout depend on the selected four-layer stackup and enclosure plastics.
Concrete Layout Instructions
  • Put U1 antenna at the upper board edge with the full Espressif all-layer keepout extending beyond/inside the edge as specified by the module datasheet.
  • Put J1 at the lower edge. Place U6 immediately behind J1; keep the pair continuous and symmetric. Place R3/R4 close to U1. No vias preferred.
  • Put U2 at the mechanical center and rotate axes to a documented product coordinate system. Keep at least several millimeters from L1/U4, USB, LEDs and button force paths.
  • Cluster U4, L1, C4–C7 tightly. Minimize the two switching loops and use a quiet Kelvin return for VINA/GND.
  • Place U3 with C1/C2/C3 and programming resistors close; connect exposed pad to a ground copper island with multiple thermal vias.
  • Use a solid inner GND plane; do not split it under USB, IMU SPI or the module. Keep SYS/BAT/3V3 paths wide and short.
  • Completion

  • Key Decisions

  • Verification Evidence

  • Production Passive MPN Groups

  • Remaining Risks

  • Concrete Layout Instructions