Dual-Node CAN Bus Design
0:04
Work done
- Built the dual-node schematic with sensor-board and DAQ-board circuits: STM32G431CBT6 MCUs, AP63203/AMS1117 power chain, 12V protection, SWD headers with 100Ω series resistors, SN65HVD230 CAN interfaces, split termination, PESD2CAN protection, hall input, OLED I2C header, and SPI SD-card header.
- Added the CAN message and hardware requirements to the project design notes.
- Configured the PCB as 80mm × 60mm, 2-layer, with JLCPCB-style baseline rules and placed all 78 components with no overlap or out-of-bounds placement issues.
- ERC checks for floating pins, no-connects, missing power, and single-pin nets are clean.
- ✅ Schematics are populated and wired for both sensor and DAQ nodes.
- ✅ PCB outline, stackup, and component placement are set up.
- ✅ CAN transceivers, split termination, and protection are included.
- ✅ CAN message format is documented.
- ❌ Final routing is not complete: the design still has 122 airwires because trace routing is the remaining physical-layout step.
Route the remaining airwires, especially CANH/CANL as a paired run and power rails at the specified widths, then rerun DRC before manufacturing export.
Review airwires
Route CAN pair
Check decoupling
Export BOM
3 days
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Dual-Node CAN Wheel Speed System Design Notes
Requirements
- Two nodes on 500 kbps CAN: sensor board and DAQ board.
- MCU on both boards: STM32G431CBT6 LQFP48, 3.3 V, internal HSI oscillator.
- Power tree on both boards: 12 V automotive input with Schottky reverse polarity protection, 15 V TVS, 100 uF bulk capacitance, AP63203WU buck to 5 V, AMS1117-3.3 LDO to 3.3 V.
- CAN physical layer on both boards: SN65HVD230 at 3.3 V, split termination, PESD2CAN protection, 3-pin CANH/CANL/GND screw terminal.
- Sensor board: JST-XH hall sensor connector powered from 5 V, PA0 input with 10 k pullup to 3.3 V and 100 nF filter to GND.
- DAQ board: SSD1306 I2C OLED on PB6/PB7 with 4.7 k pullups; SPI SD-card header on PA5/PA6/PA7/PB0 with CS pullup.
CAN Message Format
- CAN ID: 0x101
- DLC: 4 bytes
- Bytes 0-1: 16-bit RPM value
- Bytes 2-3: sequence counter
PCB Requirements
- Each board: 80 mm x 60 mm, 2-layer.
- Bottom copper: continuous GND plane.
- JLCPCB rules: 0.1 mm min trace, 0.1 mm min clearance, 0.3 mm min via drill.
- Signal traces: 0.2 mm.
- 3.3 V / 5 V traces: 0.5 mm.
- 12 V traces: 0.8 mm.
- CANH/CANL: 0.2 mm, routed together and length matched.
- Decoupling capacitors: within 1-2 mm of associated IC power pins.
Placement Rationale
- Power input protection and buck/LDO components should sit near the automotive 12 V input edge.
- SN65HVD230 should sit close to the CAN screw terminal to minimize exposed bus stub length.
- MCU decoupling and VCAP/VDDA capacitors should be placed adjacent to STM32 power pins.
- DAQ OLED and SD-card headers should sit at board edges for cable/module access.
- Sensor JST-XH hall connector should sit at a board edge with PA0 RC filter close to the MCU input path.
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