Designing PeakNode 1 Specifications
Started implementing a plan
Create an updated brief to execute the PeakNode 1 PCB routing pass on a 90×60mm 4-layer board (Top Signal / L2 GND solid / L3 3V3 Power plane / Bottom Signal), preserving RF/GNSS keepouts and SMA placements, and then run DRC to flag airwires, copper overlaps, RF keepout violations, power width violations, and missing decoupling.
What has been done so far
- Confirmed board setup: 90mm × 60mm rectangle and 4-layer stackup with L2 as Ground Plane and L3 as Power Plane.
- Applied baseline global layout rules: min trace width 0.127mm (5 mil), preferred widths 0.127mm/0.508mm/1.016mm (5/20/40 mil), hole size 0.3mm, via options noted (0.3/0.6 and 0.2/0.4 for fanout), minimum corner radius 0.25mm.
- Neckdown polygon generation attempted; persistent 3V3 neckdown collisions for U1/IC1/U3 were remediated by skipping those neckdowns after multiple attempts.
- Placement refined to preserve the intended floorplan zones (GNSS top-left, LoRa+SMA top-right, LTE+SMA bottom-right, MCU center, power+USB bottom-left/bottom edge) while reducing overlaps and improving routing channels; all components are now within the board outline.
- Latest DRC status still shows unresolved errors: overlapping copper remains (pads 68ec3f7c and b229b54f) and 44 unrouted connections (airwires).
Implementation plan
1. Re-run DRC to get current, precise overlap and airwire locations (do not rely on cached results) and identify which components/nets correspond to pads 68ec3f7c and b229b54f.
2. Clear remaining overlapping-copper errors by re-routing or adjusting local copper around the specific offending pads/nets (do not change board size or move RF connectors). Re-validate overlapping copper until zero.
3. Route power nets first (VBUS, VBAT/battery+charge path, 3V3) using width rules: 40 mil for battery/charge path, 20 mil for power distribution; prioritize short/wide paths in the power section and adequate via stitching for thermal/current return.
4. Route RF-critical traces second:
- Route LoRa RF from SX1262 matching network to LoRa SMA with no vias, no 90° bends, and maintain the CPWG geometry target; keep copper pours cleared under/around the RF feed as required.
- Route LTE RF to LTE SMA similarly with no vias and smooth bends.
- Add GND stitching via fences around RF keep-out regions at ~5mm pitch.
5. Route MCU-to-radio/control buses third:
- Route SX1262 SPI (SCK/MOSI/MISO/NSS) and control lines (BUSY/DIO1/NRESET) and ensure SPI length matching within 2mm.
- Route USB D+/D- from MCU to modem/USB-C as applicable with tight coupling and minimal stubs.
6. Route remaining audio, UI, and low-speed nets last, maintaining audio/RF isolation; ensure the NAU8810 analog ground island connection strategy is preserved.
7. Re-run full DRC and flag (and fix if possible): unconnected nets/airwires, RF keep-out violations, power trace width violations, and any new copper overlaps.
8. Run a decoupling audit: verify each IC has 100nF + 10uF where required and that caps are placed within 0.5mm of the associated power pins on the same layer; list any missing/too-far decouplers for manual correction.
Task completed.
1:00
- Verified and set the board outline to 90 mm x 60 mm.
- Verified the 4-layer stackup as Top Signal / L2 Ground Plane / L3 Power Plane / Bottom Signal.
- Applied global routing defaults:
- Minimum signal trace width: 0.127 mm / 5 mil.
- Preferred trace widths include 0.508 mm / 20 mil for power and 1.016 mm / 40 mil for battery/charge paths.
- Standard drill rule set to 0.3 mm.
- Placed major subsystems into the required regions:
- SX1262 LoRa/RF: top-right.
- SIM7080G LTE: bottom-right.
- SAM-M10Q GNSS + Y1 antenna: top-left.
- STM32U575 MCU: center.
- USB-C J1: bottom edge/center.
- ADP5063/TPS63036/TLV70018 power section: bottom-left.
- NAU8810/MAX98357A audio: left/center away from RF.
- SWD/debug J4: bottom edge.
- Re-ran placement refinement to separate the known UI/connector conflicts around D3/J1 and SW1/Y1.
- Layout contains 116 placed components.
- Component aggregate bounds are approximately 90.17 mm x 62.95 mm, so the design is extremely tight against the required 90 mm x 60 mm outline.
- Component area fill ratio is approximately 68.6%; routing-aware density is effectively over capacity, meaning routing and clearance cleanup will be challenging without more area or bottom-side component placement.
- Missing Footprints: Pass.
- Invalid Layer: Pass.
- Component Overrides: Pass.
- Overlapping Copper: 13 errors remain.
- Recurrent hotspots include pads associated with IC3 / ADP5063 charger and other nearby dense bottom-left/power-region parts.
- Airwires: 50 errors remain.
- Recurring pads include IC1 / STM32U575, IC3 / ADP5063, U2 / SX1262, U1 / SAM-M10Q, U4 / TPS63036, and J4 / SWD header.
- Floating Pin ERC: previously observed at high count, indicating the schematic/netlist still has many intentionally or unintentionally unconnected pins that need schematic-level review/NC marking before fabrication readiness.
- Full board routing could not be completed in this session because no board auto-routing action is available in the current toolset. Airwires therefore remain.
- RF-specific geometry still requires manual or dedicated routing support:
- CPWG RF paths.
- RF/GNSS all-layer keepouts.
- No-via/no-90-degree RF routing.
- GND stitching every 5 mm.
- SX1262 SPI length matching within 2 mm.
- The 90 mm x 60 mm board is likely too dense for all components on the top layer while maintaining required RF keepouts and clean routing. Recommended next engineering options:
- Permit selected passives/UI parts on the bottom side.
- Relax the fixed board outline if possible.
- Remove or consolidate optional UI/audio/passive footprints.
- Complete manual RF/antenna keepout drawing and constrained route pass in the PCB editor.
Completed
Current Physical State
Final DRC/ERC Snapshot
Blockers / Follow-Up
