Designing PeakNode 1 Specifications
Started implementing a plan
Create an updated brief to execute the PeakNode 1 PCB routing pass on a 90×60mm 4-layer board (Top Signal / L2 GND solid / L3 3V3 Power plane / Bottom Signal), preserving RF/GNSS keepouts and SMA placements, and then run DRC to flag airwires, copper overlaps, RF keepout violations, power width violations, and missing decoupling.
What has been done so far
- Confirmed board setup: 90mm × 60mm rectangle and 4-layer stackup with L2 as Ground Plane and L3 as Power Plane.
- Applied baseline global layout rules: min trace width 0.127mm (5 mil), preferred widths 0.127mm/0.508mm/1.016mm (5/20/40 mil), hole size 0.3mm, via options noted (0.3/0.6 and 0.2/0.4 for fanout), minimum corner radius 0.25mm.
- Neckdown polygon generation attempted; persistent 3V3 neckdown collisions for U1/IC1/U3 were remediated by skipping those neckdowns after multiple attempts.
- Placement refined to preserve the intended floorplan zones (GNSS top-left, LoRa+SMA top-right, LTE+SMA bottom-right, MCU center, power+USB bottom-left/bottom edge) while reducing overlaps and improving routing channels; all components are now within the board outline.
- Latest DRC status still shows unresolved errors: overlapping copper remains (pads 68ec3f7c and b229b54f) and 44 unrouted connections (airwires).
Implementation plan
1. Re-run DRC to get current, precise overlap and airwire locations (do not rely on cached results) and identify which components/nets correspond to pads 68ec3f7c and b229b54f.
2. Clear remaining overlapping-copper errors by re-routing or adjusting local copper around the specific offending pads/nets (do not change board size or move RF connectors). Re-validate overlapping copper until zero.
3. Route power nets first (VBUS, VBAT/battery+charge path, 3V3) using width rules: 40 mil for battery/charge path, 20 mil for power distribution; prioritize short/wide paths in the power section and adequate via stitching for thermal/current return.
4. Route RF-critical traces second:
- Route LoRa RF from SX1262 matching network to LoRa SMA with no vias, no 90° bends, and maintain the CPWG geometry target; keep copper pours cleared under/around the RF feed as required.
- Route LTE RF to LTE SMA similarly with no vias and smooth bends.
- Add GND stitching via fences around RF keep-out regions at ~5mm pitch.
5. Route MCU-to-radio/control buses third:
- Route SX1262 SPI (SCK/MOSI/MISO/NSS) and control lines (BUSY/DIO1/NRESET) and ensure SPI length matching within 2mm.
- Route USB D+/D- from MCU to modem/USB-C as applicable with tight coupling and minimal stubs.
6. Route remaining audio, UI, and low-speed nets last, maintaining audio/RF isolation; ensure the NAU8810 analog ground island connection strategy is preserved.
7. Re-run full DRC and flag (and fix if possible): unconnected nets/airwires, RF keep-out violations, power trace width violations, and any new copper overlaps.
8. Run a decoupling audit: verify each IC has 100nF + 10uF where required and that caps are placed within 0.5mm of the associated power pins on the same layer; list any missing/too-far decouplers for manual correction.
Task completed.
1:00
- MCU default: STM32U575 selected as the primary low-power Cortex-M33 MCU for strong low-power support, wide ecosystem, and easier external modem/radio integration.
- LTE modem default: SIM7080G selected for Cat-M1/NB-IoT plus GNSS coexistence support and broad distributor availability.
- GNSS default: u-blox M10 family selected for low-power positioning and mature ecosystem.
- Audio path default: NAU8810 selected as the codec path for LPCNet-capable audio front end.
- Power tree: USB-C 5V input -> protected VBUS -> BQ25628 charger / power-path -> battery / VSYS -> TPS63036 3.3V rail -> secondary 1.8V rail for IO domains where needed.
- Layout size: 90 mm x 60 mm
- Stackup: 4-layer
- IPC target: Class 2
- Sleep current target: under 10 uA at the system level
- RF constraints: keep-out zones under SX1262 RF region and LTE antenna region; separate noisy switching power loops from RF/GNSS sections
- Sourcing: prefer Mouser and Digi-Key, with LCSC alternates where practical
- Find exact Flux library parts for MCU, charger, regulators, modem, GNSS, LoRa radio, audio codec, USB-C, battery connector, SMA connectors, LEDs, buttons, and required passives.
- Build schematic by subsystem and wire named power and interface nets.
- Configure board size and 4-layer stackup with conservative proto rules.
Architecture decisions
Constraints
Immediate next tasks
