Waveform Generator Design with ESP32

Here’s a minimal parts list to pair an external 12-bit SPI DAC with your ESP32 for sine/saw/tri/square/multi-sine generation:

Table


RefQtyPartNotes
U11MCP4921-E/SN12-bit SPI DAC, SOIC-8
C11100nF0603VDD decoupling (X7R, 50 V)
C21GRM21BR61H106KE43LVDD bulk decoupling, 10 µF 0805 (X5R, 50 V)
R11RK73H1JTTD1002F10 kΩ 0603, 1% — DAC output filter resistor
C31100nF0603Output filter cap (together with R1)
Next, we need to place the ESP32 itself. Which variant do you prefer?
  • ESP32-S2 or ESP32-S3?
  • Do you want to use a pre-mounted module (e.g. WROOM/WROVER) or the bare QFN chip?
ESP32-S3 module
ESP32-S3 bare chip
ESP32-S2 module
ESP32-S2 bare chip
U1
U2
DN
OUT DATA
GND
DP
+5V
OUT CLOCK
SWD
SWCLK
C14
Capacitance
15pF
CN6
+3V3
+5V
+5V
+3V3
CN2
+3V3
+3V3
+3V3
C16
Capacitance
100nF
+3V3
+3V3
+3V3
+3V3
C1
Capacitance
22uF
+5V
CN1
+3V3
+5V
C3
Capacitance
1uF
C7
Capacitance
100nF
CN3
C11
Capacitance
100nF
+1V1
C6
Capacitance
100nF
CN7
+5V
CN8
+5V
C9
Capacitance
100nF
CN4
CN5
C13
Capacitance
100nF
C12
Capacitance
100nF
C10
Capacitance
100nF
+5V
C2
Capacitance
22uF
+1V1
C15
Capacitance
15pF
C4
Capacitance
1uF
C5
Capacitance
100nF
C8
Capacitance
100nF
USB_HID_DP
QSPI_SD3
PS2_Barcode_IN_Clock
R16
Resistance
1kΩ
QSPI_SD3
QSPI_SCLK
QSPI_SD2
R3
Resistance
27.4 Ω
PS2_POS_OUT_Data
PS2_Barcode_IN_Data
RX_OUT
R2
Resistance
27.4 Ω
QSPI_SD1
USB_HID_DN
QSPI_SD0
R13
Resistance
10kΩ
R15
Resistance
10kΩ
QSPI_SD1
QSPI_SS
TX_OUT
TX_OUT
R7
Resistance
10kΩ
PS2_Barcode_IN_Data
PS2_POS_OUT_Clock
R4
Resistance
1kΩ
R11
Resistance
10kΩ
R10
Resistance
10kΩ
U1TXD
QSPI_SD2
R9
Resistance
10kΩ
RX_OUT
R12
Resistance
10kΩ
R6
Resistance
0 Ω
PS2_POS_OUT_Data
QSPI_SD0
R8
Resistance
10kΩ
R14
Resistance
10kΩ
R5
Resistance
0 Ω
PS2_POS_OUT_Clock
U1RXD
QSPI_SS
R1
Resistance
10kΩ
QSPI_SCLK
PS2_Barcode_IN_Clock
Y1
Q4
PS1
Q3
U3
Q1
Q2

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Documents

    Documents are markdown text files which describe project goals, capture details, or even simulation outputs.

    Assets

    nv_logo.svg

    nv_logo.svg

    nv_logoDefault
    multi-layer-thumb.png

    multi-layer-thumb.png

    multi-layer-thumbThumbnail

    DoverCheck/PS2_Both_Side 5zCC

    DoverCheck/PS2_Both_Side 5zCC thumbnail
    Use this template if you're planning to get your multi layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules

    Properties

    1.6

    mm

    LCSC

    Pricing & Availability

    Distributor

    Qty 1

    Controls