Board Bring-Up Plan
Safety and source requirement
Use a dedicated compliant USB-C 5 V/3 A source and cable. Verify at least 4.75 V at J1 under the design load. Do not use a default-current host port as the main supply. Leave LED, ToF, remote IMU and Pi disconnected for initial tests.
1. Visual and unpowered checks
- Inspect U1/U2/U4/U5/U6 orientation and exposed pads.
- Confirm L1 is XAL7030-222MEC and C7/C11/C12/C23/C24 are the specified Murata 22 µF/25 V/X7R/1210 parts. L1's datasheet values are Isat 18.0 A, 10.0 A for 20 °C rise, and 12.9 A for 40 °C rise.
- Measure resistance from VBUS_RAW, protected 5V and 3V3 to GND.
- Verify J2 VBUS has no DC continuity to 3V3, protected 5V, GPIO2 or D+/D−; it may show only the R43/U6 LED path to ground.
2. Main power and eFuse
- Apply 5.0 V with a 0.2 A current limit, then raise gradually.
- Verify TP1 protected 5 V and TP13 eFuse fault.
- Load the system to the 1.12 A design point and verify J1 remains at or above 4.75 V.
- Confirm reverse-current blocking toward J1.
3. Buck regulator
- Verify TP2 = 3.3 V and TP12 PG is high.
- Check startup, ripple and overshoot.
- Load-test 0.25 A and 0.70 A; 1.2 A is an optional margin test. Monitor U2 and L1 temperature.
- Verify all four output capacitors are fitted. The conservative estimated effective output bank is 47.56 µF; measured ripple target is below approximately 10 mV p-p under steady design load, compared with the 4.1 mV calculated capacitor/ESR contribution.
- Check the protected-5V input directly at U2 during load steps. C7's conservative effective value is 11.89 µF at 5 V, above the 10 µF minimum, with C8 providing the mandatory 220 nF local bypass.
- Capture startup at maximum expected load and a 0-to-0.68 A output load step; reject sustained oscillation, PG chatter, excessive droop, or overshoot above 3.6 V.
4. ESP32 and programming
- Verify EN/BOOT controls and UART recovery.
- Program over native USB only while J1 independently powers the board.
5. USB back-power test
- With J1 absent, connect J2 to a Pi/PC. Confirm protected 5 V and 3V3 remain at 0 V and the ESP32 does not partially power.
- With J1 present and J2 absent, confirm J2 VBUS is 0 V.
- With both connected, confirm USB enumeration and that TP16/
USB_VBUS_PRESENT_N is low.
- Disconnect J2 and confirm TP16 returns high from R44. This is a digital active-low test, not an ADC-voltage test.
- Inspect D+/D− eye/rise behavior if enumeration is unstable; D2 is a 0.7 pF rail-less TVS.
6. IMU
- Read WHO_AM_I with only on-board CS active.
- Confirm INT1/INT2 idle high through R41/R42 before configuration.
- Configure active-low open-drain and verify interrupt pulses.
- Test the remote unit at reduced SPI clock and prove that only one CS is active; verify no MISO contention.
- With the board unpowered, do not apply signals or external 3V3 through J3. D3-D5 are rail-clamped to board 3V3 and can back-inject current.
7. ToF carrier
- Confirm J4 pin 1 = 3.3 V and connector pitch is 1.25 mm JST-GH.
- Keep R28/R29 DNP for the official SATEL carrier unless pull-up measurements justify otherwise.
- Verify SDA/SCL, LPn and INT operation; D9 protects LPn/INT.
- The carrier must be powered from this board. Do not externally drive SDA/SCL while this board is off because D6 can inject into unpowered 3V3.
8. LED driver and headroom
- Use only one characterized white LED with Vf no greater than 3.6 V at 250 mA.
- Use a harness no longer than 30 cm and verify total harness/connector drop no greater than 0.15 V at full current.
- Confirm output is OFF during power-up, reset, bootloader and firmware reset.
- Increase PWM duty gradually; expected nominal current is 250 mA and worst-case upper current from reference tolerance is approximately 260 mA.
- At minimum input condition, verify J1 >=4.75 V and LED current remains regulated. Reject any module that exceeds the voltage/drop limits.
- Monitor U5 temperature and fault output. Series LED strings are prohibited.
9. ESD-exposed interfaces
- Verify UART and sync function after D10/D11 installation.
- J7 SYNC_SPARE and J6 EN/BOOT are unprotected bench-only nodes; use only short local jumpers and no hot-plugging.
- J8 exposed 5V/3V3 rails and GPIO38/39/40 are unprotected. J8 is limited to short bench jumpers, with no independent external drive or hot-plugging.
Pass criteria
- No rail rise or partial powering from J2 alone.
USB_VBUS_PRESENT_N correctly reports host presence.- 5 V and 3.3 V remain stable under design loads.
- IMU interrupts idle and operate correctly with open-drain pull-ups.
- ToF, UART and sync interfaces function through their protection arrays.
- LED remains default OFF and regulates only with a compliant LED module/source/harness.
- No unexplained eFuse, buck PG, LED fault or thermal event.