Custom USB Switch Design

The schematic is electrically back in a clean, verified state: all intended USB, power, MCU, CC, and control nets are intact, and ERC shows no open errors or warnings. I rolled back the unsafe cleanup attempt and preserved the working design rather than risking hidden connectivity damage.
Open items:
  • The remaining messy visual labels are platform-generated portal labels that did not persist when renamed through the available schematic edit path.
Suggested next steps:
  1. Proceed to PCB layout from the verified netlist.
  2. Add status LEDs before layout if desired.
  3. If visual schematic cleanup is still important, use the schematic editor manually to relabel/group portals, since the automated rename path did not stick.
Yes, move on to PCB layout from the verified netlist.
I’ll move into PCB layout: set up an appropriate USB 2.0 board/stackup, place the connectors/mux/protection/power/control parts, route the critical USB pairs, then run layout checks.
Processing was stopped.
Here's a summary of what I was working on: Troubleshooting PCB layout issues
I need to address the USB_A pins, which might be blocked due to the connector placement being too far out of bounds. The current board dimensions might need resizing, perhaps to 75x50 or even 80x55, to avoid this issue. I also have to consider the existing routes; they might get messy if I change the layout or need to delete dangling connections after rerouting. I’ll definitely check the history to revert to a workable state before the auto-route.
Check USB routing
Inspect 3V3 clearance
Widen power traces
Optimize placement
J5
J3
D2
D1
J1
J2
J4
J4 EH - U3 GND
J4 EH - U3 GND
J4 EH - U3 GND
J1 GND - J1 GND__1
GND
J4 EH - U3 GND
J1 GND - J1 GND__1
J1 GND - J1 GND__1
J1 GND - J1 GND__1
J4 EH - U3 GND
J4 EH - U3 GND
J4 EH - U3 GND
J4 EH - U3 GND
J1 GND - J1 GND__1
J1 GND - J1 GND__1
J1 GND - J1 GND__1
J1 GND - J1 GND__1
J4 EH - U3 GND
J1 GND - J1 GND__1
J4 EH - U3 GND
J4 EH - U3 GND
J4 EH - U3 GND
J4 EH - U3 GND
J4 EH - U3 GND
J1 GND - J1 GND__1
J4 EH - U3 GND
J1 GND - J1 GND__1
J1 GND - J1 GND__1
J4 EH - U3 GND
J4 EH - U3 GND
GND
J1 GND - J1 GND__1
J4 EH - U3 GND
J1 GND - J1 GND__1
J4 EH - U3 GND
J4 EH - U3 GND
J1 GND - J1 GND__1
J1 GND - J1 GND__1
J1 GND - J1 GND__1
J1 GND - J1 GND__1
J4 EH - U3 GND
J4 EH - U3 GND
J4 EH - U3 GND
C7
Capacitance
150uF
U2 PB1 - U1 ~{OE}
U4 OUT - J3 VBUS
J1 DP1 - J1 DP2
J3 DP1 - J3 DP2
J2 DP1 - J2 DP2
J2 DN1 - J2 DN2
U2 AREF/PB0 - U1 S
C4
Capacitance
100nF
J3 DN1 - J3 DN2
J1 DP1 - J1 DP2
J2 DN1 - J2 DN2
J1 CC1 - R1 P1
J4 VBUS - U3 IN
U3 OUT - U1 VCC
J4 CC1 - R5 P1
U2 XTAL2/PB4 - U4 EN
J3 DP1 - J3 DP2
J3 CC2 - R8 P2
U2 AREF/PB0 - U1 S
U3 OUT - U1 VCC
J1 VBUS__1 - D1 VBUS
J3 DP1 - J3 DP2
U2 ~RESET~/PB5 - J5 RST
J2 CC1 - R3 P1
U2 PB1 - U1 ~{OE}
U2 XTAL1/PB3 - SW1 1
J1 VBUS__1 - D1 VBUS
J2 DP1 - J2 DP2
U3 OUT - U1 VCC
U4 EN - C1 P1
U4 EN - C1 P1
U2 PB1 - U1 ~{OE}
U2 XTAL2/PB4 - U4 EN
U2 AREF/PB0 - U1 S
U3 OUT - U1 VCC
U4 EN - C1 P1
J3 DP1 - J3 DP2
U4 EN - C1 P1
J2 DN1 - J2 DN2
J1 DN1 - J1 DN2
C2
Capacitance
2.2uF
C3
Capacitance
10uF
J2 CC2 - R4 P1
J1 DN1 - J1 DN2
C6
Capacitance
100nF
U2 XTAL2/PB4 - U4 EN
J1 CC1 - R1 P1
J1 DP1 - J1 DP2
U4 EN - C1 P1
C5
Capacitance
100nF
U4 EN - C1 P1
J1 DN1 - J1 DN2
J1 DN1 - J1 DN2
J2 DN1 - J2 DN2
U4 OUT - J3 VBUS
U2 PB1 - U1 ~{OE}
J2 DP1 - J2 DP2
J3 DN1 - J3 DN2
U3 OUT - U1 VCC
J2 DP1 - J2 DP2
J1 DP1 - J1 DP2
J4 CC1 - R5 P1
J4 VBUS - U3 IN
U2 XTAL1/PB3 - SW1 1
U2 PB2 - J5 SCK
U4 EN - C1 P1
J4 CC2 - R6 P1
J3 VBUS__1 - C7 P1
J4 CC2 - R6 P1
U2 ~RESET~/PB5 - J5 RST
J3 DN1 - J3 DN2
U2 AREF/PB0 - U1 S
J2 CC1 - R3 P1
U2 PB2 - J5 SCK
U3 OUT - U1 VCC
U3 OUT - U1 VCC
U2 ~RESET~/PB5 - J5 RST
U2 XTAL1/PB3 - SW1 1
J2 DN1 - J2 DN2
J2 VBUS__1 - D2 VBUS
U3 OUT - U1 VCC
J1 CC2 - R2 P1
J2 VBUS__1 - D2 VBUS
J2 DP1 - J2 DP2
J3 CC1 - R7 P2
J1 DN1 - J1 DN2
J3 VBUS__1 - C7 P1
U3 OUT - U1 VCC
C1
Capacitance
1uF
J2 CC2 - R4 P1
J3 DN1 - J3 DN2
J1 CC2 - R2 P1
J3 CC1 - R7 P2
U3 OUT - U1 VCC
J1 DP1 - J1 DP2
J3 CC2 - R8 P2
U4
R9
Resistance
10kΩ
R7
Resistance
56kΩ
R8
Resistance
56kΩ
R1
Resistance
5.1kΩ
R11
Resistance
100kΩ
SW1
R2
Resistance
5.1kΩ
R4
Resistance
5.1kΩ
R6
Resistance
5.1kΩ
U2
R12
Resistance
100kΩ
R10
Resistance
10kΩ
R13
Resistance
100kΩ
R3
Resistance
5.1kΩ
U3
R5
Resistance
5.1kΩ
U1

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Project Specification — USB 2.0 Host Switch
Project Overview
Status: Draft
This project is an externally powered USB 2.0 high-speed switchbox. It connects one downstream self-powered USB hub to exactly one of two USB-C host computers at a time. The primary reliability goal is stable switching for USB audio devices, especially avoiding bad re-enumeration behavior where a DAC falls back to an incorrect low-speed mode and produces distorted audio.
Intended Use
The device sits between two computers and a self-powered external USB hub. The hub carries console/peripheral devices including a keyboard, mouse, DAC, microphone, and webcam. The user presses a button on the switchbox to move the hub connection from one computer to the other.
This is a prototype/validation design, not yet production-approved.
What the Device Should Do
  • Switch one USB 2.0 high-speed downstream hub connection between two upstream host computers.
  • Support USB 2.0 high-speed operation at 480 Mb/s.
  • Use USB-C connectors for host and hub connections.
  • Use an external power supply so control logic and hub-side attach signaling remain stable during switching.
  • Perform a deliberate break-before-make switching sequence.
  • Avoid tying the two host computers’ VBUS rails together.
  • Keep the self-powered hub logically attached in a clean, repeatable way.
Main Features
  • Two USB-C host-side upstream connectors: Host A and Host B.
  • One USB-C hub-side downstream connector.
  • External 5 V power input for switchbox logic and hub-side VBUS-present signaling.
  • USB 2.0 high-speed differential data switch.
  • Pushbutton user interface.
  • Microcontroller-controlled switch sequencing.
  • ESD protection on exposed USB D+/D− lines.
  • 3.3 V logic rail for controller and USB switch IC.
System Architecture

Diagram


Host A USB-C USB 2.0 HS D+/D- Mux Host B USB-C Hub USB-C Upstream Port External 5 V Input 3.3 V LDO Microcontroller Pushbutton Current-limited hub-side VBUS
Hardware Subsystems
USB Data Switching
A USB 2.0 high-speed analog mux switches D+ and D− between Host A and Host B. The mux is controlled by the microcontroller. The routing and PCB layout must treat D+ and D− as 90 Ω differential pairs with short traces, minimal stubs, and continuous ground reference.
USB-C Role Handling
  • Host A and Host B connectors act as USB-C device/UFP-facing ports toward the computers and use Rd pull-downs on CC1 and CC2.
  • Hub connector acts as a USB-C host/DFP-facing port toward the hub and uses Rp pull-ups on CC1 and CC2.
  • Host VBUS rails are sensed/available only for attach awareness if needed; they are not tied together and are not used to power the switchbox.
  • Hub-side VBUS-present is supplied from the switchbox external 5 V rail through a current-limited switch. The microcontroller controls this switch so firmware can deliberately cycle hub-side attach signaling during switching if testing shows the hub or DAC needs it.
Control Logic
A small microcontroller reads the pushbutton, controls the USB data switch, and controls the hub-side VBUS switch. Firmware implements:
  1. Debounce pushbutton.
  2. Disconnect current host path.
  3. Wait a defined detach interval, initially 250 ms.
  4. Optionally cycle hub-side VBUS-present for a clean hub attach event.
  5. Connect the alternate host.
  6. Optionally expose status LED outputs in a later revision.
Power
The switchbox is powered from an external 5 V supply. A 3.3 V LDO powers the microcontroller and USB switch. The downstream hub is self-powered; the switchbox only provides hub-side VBUS-present/current-limited 5 V if required for USB attach behavior.
Protection
Each externally exposed USB D+/D− pair should include low-capacitance ESD protection close to the USB-C connector. Power input should include basic input capacitance and optional fuse/TVS protection in later revisions.
Interfaces and Connections

Table


InterfaceConnectorRoleNotes
Host AUSB-C receptacleUFP/device-facingConnects to computer A
Host BUSB-C receptacleUFP/device-facingConnects to computer B
HubUSB-C receptacleDFP/host-facingConnects to self-powered downstream hub
Power InputUSB-C power or DC input5 V inputPowers switchbox logic
Switch ButtonTactile pushbuttonUser inputInitiates host toggle
ProgrammingHeader/padsMCU programmingRequired for firmware loading
Power and Runtime Expectations
  • External supply: 5 V nominal.
  • Logic rail: 3.3 V.
  • Expected switchbox current: low, likely under 100 mA excluding any hub-side VBUS-present load.
  • No battery operation planned.
  • Device should remain powered continuously independent of selected host.
Power Tree and Power Budget

Table


RailSourceLoadsEstimated Current
5V_EXTExternal 5 V input3.3 V LDO, current-limited hub-side VBUS switchTBD, design target ≥1 A available for fault margin
3V3LDO from 5V_EXTMCU, USB mux, pull-ups/status LEDs<100 mA expected
VBUS_HUBTPD3S014 from 5V_EXTHub-side VBUS-present500 mA continuous target, current-limit fault testing required
HOST_A_VBUSHost ASense/ESD onlyNo load intended
HOST_B_VBUSHost BSense/ESD onlyNo load intended

Diagram


External 5 V Input protection / optional fuse 5V_EXT 3.3 V LDO 3V3 MCU USB HS Mux TPD3S014 current-limited switch VBUS_HUB
Manufacturing and Assembly Expectations
  • SMD prototype design.
  • Prefer common, currently available ICs and connectors.
  • USB 2.0 high-speed routing should use a 4-layer PCB for controlled impedance and solid ground reference.
  • Add test points for 5V_EXT, 3V3, GND, switch select, and MCU programming signals.
Firmware-Relevant Hardware Requirements
  • GPIO for USB mux select.
  • GPIO for USB mux enable/output disconnect if available.
  • GPIO for hub-side VBUS switch enable.
  • GPIO input for pushbutton with pull-up.
  • Programming/debug header or pads for the selected MCU.
  • Optional future GPIOs for Host A / Host B status LEDs.
Physical Design Expectations
  • Connector placement should support intuitive cabling: Host A and Host B on one side, hub and power on the other side if practical.
  • Keep USB data switch physically close to the USB-C connectors to minimize high-speed trace length and stubs.
  • ESD devices should be placed close to connector pins.
  • Board size is not fixed yet.
Important Design Decisions
  • Use an externally powered switchbox rather than bus-powered switching.
  • Use one self-powered downstream hub; the switchbox does not integrate the hub in Rev 1.
  • Switch only USB 2.0 D+/D− at 480 Mb/s, not USB 3.x SuperSpeed.
  • Use controlled break-before-make switching to improve DAC re-enumeration reliability.
  • Make hub-side VBUS-present MCU-controlled rather than always-on, so firmware can test whether cycling attach signaling improves DAC/hub recovery.
  • Avoid connecting Host A VBUS to Host B VBUS or to the switchbox supply.
Assumptions
  • The downstream hub has its own stable power supply.
  • The hub uses USB 2.0 high-speed devices or can fall back through USB 2.0 even if the physical connector is USB-C.
  • The webcam can operate acceptably over USB 2.0 through the external hub.
  • The first revision can use firmware for sequencing.
  • Exact enclosure and board size are TBD.
Change Notes
  • Initial draft created from user requirements.
  • Simplified architecture from multi-device switch to one USB 2.0 high-speed port/hub switch.
  • Added externally powered control logic and break-before-make switching requirement to address DAC transition instability.
  • Added MCU-controlled hub-side VBUS switch enable after review, improving attach sequencing control and reducing always-on source-port risk.
  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • USB Data Switching

  • USB-C Role Handling

  • Control Logic

  • Power

  • Protection

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes

Documents

  • Project Specification — USB 2.0 Host Switch

  • Firmware Starter — ATTINY85V-10SU

  • Board Bring-Up Plan — USB 2.0 Host Switch

Assets

No assets added.

USB 2.0 Host Switch

USB 2.0 Host Switch thumbnail
Externally powered USB 2.0 high-speed switch that toggles one downstream self-powered hub between two USB-C host computers with stable break-before-make switching for USB audio reliability.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$1.67–$3.12

Digi-Key

$4.02–$4.25

HQonline

$5.41–$5.61

LCSC

$8.39–$8.64

Mouser

$6.80

TME

$5.20

Verical

$4.07–$6.75

Controls