The schematic is electrically back in a clean, verified state: all intended USB, power, MCU, CC, and control nets are intact, and ERC shows no open errors or warnings. I rolled back the unsafe cleanup attempt and preserved the working design rather than risking hidden connectivity damage.
Open items:
- The remaining messy visual labels are platform-generated portal labels that did not persist when renamed through the available schematic edit path.
Suggested next steps:
- Proceed to PCB layout from the verified netlist.
- Add status LEDs before layout if desired.
- If visual schematic cleanup is still important, use the schematic editor manually to relabel/group portals, since the automated rename path did not stick.