• Portable field instrument powered by common 45W or higher USB-C PD power banks.
• Simultaneous capture on three independent Wi-Fi 7 radios.
• Passive surveys, packet capture, channel analysis, and GNSS-tagged measurements.
• Optional HackRF One or similar SDR on an independently powered USB 3 port.
• Production-oriented enclosed assembly with internal low-profile antennas and external RF test options.

• Raspberry Pi Compute Module 5, preferably 8GB RAM and 32GB eMMC.
• Three M.2 2230 E-key sockets for MT7925B22M-class modules.
• PCIe Gen2 packet switch providing one x1 link to each radio.
• Two native CM5 USB 3 ports: one dedicated to SDR and one service/expansion port.
• Multi-constellation GNSS with UART and 1PPS.
• USB-C PD input, 45W operating target, and 5V rail sized for 8A transients.
• Independent radio power switching, current monitoring, reset, disable, and fault reporting.
• Auxiliary controller for power sequencing, fan control, watchdog, and user controls.
• Six antenna chains with low-profile internal antennas and accessible coax test paths.

Diagram

• Four Cortex-A76 cores at up to 2.4GHz provide significantly more packet-processing headroom.
• Two independent native USB 3 ports can each signal at 5Gb/s.
• The SDR no longer consumes the only PCIe link through a PCIe-to-USB bridge.
• One PCIe Gen2 x1 host remains available exclusively for the three-radio PCIe switch.
• The CM5 carrier pinout retains broad CM4 mechanical compatibility, but USB 3 uses repurposed CAM0 and DSI0 pin groups and the carrier is intentionally CM5-only.

• Three standard MT7925 M.2 E-key modules.
• WLAN uses PCIe, as required by currently available MT7925B22M modules.
• Bluetooth USB 2.0 interfaces are not populated in revision A unless later required.
• Each radio receives one independent downstream PCIe x1 link.
• The shared upstream CM5 link is PCIe Gen2 x1.

• One fixed x1 upstream port and three fixed x1 downstream ports.
• PCIe Gen2 at 5GT/s per lane.
• Integrated three-output 100MHz PCIe reference-clock buffer.
• Dedicated downstream reset outputs.
• Strap, EEPROM, or SMBus configuration.
• 128-pin 14mm LQFP package, practical for prototype assembly and inspection.
• Requires 3.3V and 1.0V rails with controlled sequencing.

• USB 3 port 0: dedicated powered SDR port, minimum 1.5A configurable current limit.
• USB 3 port 1: service/expansion port, suitable for storage, debug capture, Ethernet, or a future USB-native Wi-Fi adapter.
• Both ports receive ESD protection and independent current-limited 5V load switches.
• The CM5 shared VBUS enable is buffered into independently controllable port power paths.
• A separate USB 2 OTG/service connection may be retained for CM5 provisioning and recovery.

• USB-C Power Delivery sink.
• Preferred fixed PDO: 15V at 3A.
• Minimum full-performance source: 45W.
• A 20V contract may be supported only if every downstream power-path component is rated appropriately.
• Reduced-power firmware mode may operate from 30W sources by disabling the SDR port and staggering radio startup.

• Autonomous PD sink operation without relying on the CM5 to boot.
• NVM-configurable sink PDOs.
• External high-current VBUS path control.
• Up to 20V/5A capability with a suitable connector, cable, MOSFETs, protection, and board copper.

• 15V nominal input to a synchronous buck regulator.
• 5.1V nominal output at the converter, allowing controlled distribution loss while remaining within CM5's 4.75V to 5.25V input range.
• 6A continuous thermal design target; 8A transient capability.
• Regulator silicon should be rated 10A or higher for thermal and transient margin.
• Use a low-EMI regulator or spread-spectrum mode, shielded inductor, compact hot loop, and shield-can provision.
• Include input eFuse/hot-swap protection, reverse blocking, TVS, current/voltage monitoring, and temperature sensing.

• 5V to 3.3V, 6A continuous minimum and 8A transient design target.
• Lower total switching noise, fewer inductors near antennas, and better efficiency.
• Three independent low-resistance load switches downstream.
• Each radio branch includes current limiting, quick output discharge, fault indication, bulk capacitance, ferrite filtering, and telemetry.
• M.2 radio power pins receive 3.3V only; 5V is never applied to the cards.

• 1.0V rail for the PCIe switch core and analog domains.
• Quiet 3.3V rail or filtered branch for GNSS and control circuitry.
• Standby 3.3V rail for the RP2040 supervisor if independent shutdown control is required.

• Full survey plus SDR: 45W source required; service USB current may be limited.
• Three-radio survey without SDR: expected 22-28W source demand depending on CPU and radio activity.
• Reduced-power mode: two radios or reduced CM5 performance for 20-30W sources.
• Boot sequencing: supervisor starts CM5 first, then enables radio branches individually after the 3.3V rail is stable, preventing simultaneous inrush.

• Multi-constellation receiver suitable for survey geotagging.
• UART to CM5 for NMEA/UBX data.
• 1PPS/time-pulse signal to a CM5 GPIO for timestamp correlation.
• External active GNSS antenna connector with antenna bias, current limiting, ESD protection, and optional passive antenna support.
• Dedicated quiet filtered supply and physical separation from DC/DC inductors, USB 3, PCIe, and Wi-Fi antennas.

• Sequence CM5 and the three radio power branches.
• Read radio current monitors, rail voltages, and thermal sensors.
• Control fan speed and status LEDs.
• Handle power button, graceful shutdown request, and forced shutdown timeout.
• Report faults to CM5 through I2C or UART.
• Provide an external watchdog capable of resetting or power-cycling the CM5.
• Allow firmware-controlled reduced-power modes based on the negotiated PD contract.

• Use the M.2 modules' native MHF4 connectors with short, controlled-bend micro-coax assemblies.
• Provide six internal low-profile tri-band FPC or stamped antennas distributed around the enclosure perimeter.
• Provide accessible coax test paths or optional bulkhead connectors for development; avoid permanent cascaded MHF4-to-u.FL adapters in production where insertion loss is unnecessary.
• Place the three radio modules along the board perimeter and separate each antenna pair spatially.
• Use cross-polarized or orthogonally oriented antenna pairs where the enclosure permits.
• Keep antennas clear of the CM5 heat spreader, battery/power bank, shield cans, USB cables, and user grip zones.
• Place CM5, PCIe switch, USB 3 routing, oscillators, and switch-mode power under grounded shield-can regions.
• Retain one continuous ground reference plane; do not use ground splits beneath PCIe or USB pairs.
• Keep DC/DC switch nodes and inductors away from all antenna feeds and the GNSS section.

• Eight-layer controlled-impedance PCB minimum.
• Recommended layer strategy: signal / ground / signal / power / power / signal / ground / signal, refined with the fabricator for 85-ohm PCIe and 90-ohm USB differential impedance.
• CM5 and main buck converter require direct thermal coupling to an aluminum enclosure or internal heat spreader.
• Radio modules should have airflow and shield-clearance while keeping antennas away from hot metal.
• Board should include mounting points that prevent M.2 and coax flex during field handling.
• USB-C, SDR USB, service USB, power button, GNSS antenna, and debug connectors belong on enclosure edges.
• Initial enclosure size should prioritize antenna spacing and thermal performance rather than minimum board area.

• Use a recent 64-bit Raspberry Pi kernel with mt76, mt7925e, and required firmware blobs.
• Device tree must enable the PCIe root port, both native USB 3 interfaces, UART, PPS GPIO, supervisor interface, and any fan/thermal controls.
• Bind stable logical radio names using PCIe topology or module serial/MAC data.
• Log PD contract, branch current, rail faults, and thermal state with survey records.
• Support selective radio reset and power cycle without rebooting the CM5.
• Validate simultaneous monitor mode, radiotap field completeness, packet loss, channel switching, and recovery after PCIe errors.

• Production-intent SMT assembly; not intended for hand soldering.
• High-Tg controlled-impedance laminate and ENIG finish preferred.
• Include boundary-scan or accessible test points for critical power, reset, clock, UART, I2C, and PCIe status signals.
• Provide fixture access for CM5 provisioning, supervisor programming, and radio branch load testing.
• Use components with active lifecycle and multi-source passives where possible.
• Prototype with shield-can footprints even if cans are not fitted on the first spin.

1. Replace CM4 with CM5.
2. Use PCIe, not USB, for all three M.2 Wi-Fi radios.
3. Use PI7C9X2G404SL as the three-way PCIe Gen2 fanout.
4. Reserve native CM5 USB 3 port 0 for the SDR and port 1 for service/expansion.
5. Use 45W USB-C PD as the full-performance input requirement.
6. Build a 5V rail for 6A continuous and 8A transient operation.
7. Use one central high-current 3.3V radio regulator plus per-radio protected load switches.
8. Use MAX-M10S GNSS with UART and 1PPS.
9. Add an RP2040 power-management supervisor.
10. Use an eight-layer RF-conscious PCB with enclosure heat spreading.

• Driver risk: Confirm the exact MT7925 module and Linux build provide required monitor mode and radiotap metadata.
• PCIe enumeration risk: Prototype the CM5 plus PI7C9X2G404SL topology before committing the complete carrier layout if possible.
• Shared PCIe bandwidth: Measure packet loss under simultaneous high-rate capture on all radios.
• Power uncertainty: Bench-measure radio transient current with the exact selected module; public maximum-current data is incomplete.
• RF self-interference: Conduct simultaneous-radio OTA testing, especially when radios occupy adjacent or harmonically related channels.
• Thermal risk: Validate sustained CM5 CPU load, three active radios, and SDR operation in the final sealed enclosure.
• Power-bank compatibility: Test representative Anker 45W, 65W, and 100W models, including startup, renegotiation, cable removal, and low-load behavior.

1. CM5 connectors, boot, eMMC service, clocks, and required power pins.
2. USB-C PD input, protection, and 15V-to-5V main converter.
3. PCIe switch, 1.0V supply, clocking, straps, EEPROM option, and resets.
4. Three M.2 E-key sockets with PCIe, 3.3V branch protection, and radio control.
5. Native USB 3 SDR and service ports with protection and power switching.
6. GNSS, antenna bias, UART, and PPS.
7. RP2040 supervisor, telemetry, thermal control, buttons, and indicators.
8. Test points, programming interfaces, and manufacturing provisions.

• Architecture revised from CM4 to CM5 for substantially higher CPU performance and two native USB 3 ports.
• Removed VL805 and USB 3 hub from the primary architecture.
• Selected PI7C9X2G404SL for one-upstream/three-downstream PCIe fanout.
• Increased full-performance source target to 45W USB-C PD.
• Consolidated radio conversion into one central high-current 3.3V rail with independently switched branches.
• Added RP2040 board-management controller and selected MAX-M10S GNSS.