Learn how to use AI Auto Layout on this ESP32 Espresso Smart Scale! In one click you’ll see AI Auto Layout perform magic. Pay close attention to how we recommend creating rulesets, zones, and fanouts. By copying the setup in this example on your own project, you’ll have a fully routed board in no time!
Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules
ESP32 8 Relay Board. Has onboard mains to 5V or can use the ESP VIN for the +5V. 8 onboard relays capable of switching about 5A without adding additional tin to the traces.
Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules
Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules
Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules
ESP32 8 Relay Board. Has onboard mains to 5V or can use the ESP VIN for the +5V. 8 onboard relays capable of switching about 5A without adding additional tin to the traces.
ESP32 8 Relay Board. Has onboard mains to 5V or can use the ESP VIN for the +5V. 8 onboard relays capable of switching about 5A without adding additional tin to the traces.
![ESPRSSO32 Smart Scale AI Auto Layout [Example]](https://img-cdn.flux.ai/eyJidWNrZXQiOiJncmF2aXRvbi1lbGVjdHJpYy1zeW1ib2xzIiwia2V5IjoiZG9jdW1lbnRfYXNzZXRzL0VTUFJFU1NPMzJfU21hcnRfU2NhbGVfM0RfVGh1bW5haWwtY2QxNTI2NjItNjdjMi00MTk4LWJmNjUtNDJiZDk5N2E0ODYyLnBuZyIsImVkaXRzIjp7InJlc2l6ZSI6eyJ3aWR0aCI6NjQsImhlaWdodCI6NjQsImZpdCI6ImNvbnRhaW4iLCJiYWNrZ3JvdW5kIjp7InIiOjAsImciOjAsImIiOjAsImFscGhhIjowfX19LCJvdXRwdXRGb3JtYXQiOiJ3ZWJwIn0=)
![[2-layer] JLCPCB Constraints 9PQK](https://img-cdn.flux.ai/eyJidWNrZXQiOiJncmF2aXRvbi1lbGVjdHJpYy1zeW1ib2xzIiwia2V5IjoiZG9jdW1lbnRfYXNzZXRzLzItbGF5ZXItdGh1bWItYzk4NzE0NGEtNTg0Ni00MzEyLTlkNDktNjBlZmM2N2FiMDk3LnBuZyIsImVkaXRzIjp7InJlc2l6ZSI6eyJ3aWR0aCI6NjQsImhlaWdodCI6NjQsImZpdCI6ImNvbnRhaW4iLCJiYWNrZ3JvdW5kIjp7InIiOjAsImciOjAsImIiOjAsImFscGhhIjowfX19LCJvdXRwdXRGb3JtYXQiOiJ3ZWJwIn0=)
