Project Getting Started


I’ll continue by repairing the PCB placement overlaps first, verify DRC, then route and recheck the board if the layout is ready.
Placement is now clean: all 17 copper overlaps are resolved, and the ESP32 antenna and USB-C edge access are preserved. I’m running routing preflight now, then I’ll route the board and clean up any residual issues.
Routing preflight is improved: all width-versus-pad errors are cleared, with scoped fine-pitch neckdowns and no global clearance reduction. Some footprint-internal pad-access warnings remain, so I’m proceeding with routing and will address the exact residual connections afterward.
Placement is repaired and all 17 copper-overlap errors are cleared. Scoped fine-pitch rules were added, and auto-routing placed 780 traces/vias, reducing airwires from 159 to 39.
Open items
  • 39 airwires remain around J1/D1 USB, U2 CP2102, U4 power mux, and Q1.
  • Final DRC and targeted fanout cleanup remain.
  • Execution stopped because no ACUs are currently available.
Next step
  1. Add ACUs.
  2. Resume targeted routing cleanup.
  3. Run final DRC and verify zero blocking errors.
Add ACUs guidance
Prioritize remaining airwires
Manual routing guidance

D1
U5
U3
J1
U1
Q1
U2
C2
Capacitance
1uF
R25
Resistance
100Ω
TP10
R23
Resistance
33Ω
D3
L2
Inductance
3.9uH
C13
Capacitance
100uF
C9
Capacitance
10nF
TP5
R30
Resistance
10kΩ
C4
Capacitance
100nF
Q3
R9
Resistance
47.5kΩ
R20
Resistance
4.7kΩ
TP6
R13
Resistance
23.7kΩ
TP9
R29
Resistance
100Ω
C3
Capacitance
4.7uF
R8
Resistance
22.1kΩ
R1
Resistance
10kΩ
R26
Resistance
100Ω
R12
Resistance
49.9kΩ
R7
Resistance
1kΩ
C8
Capacitance
100nF
TP7
R18
Resistance
5kΩ
C6
Capacitance
33uF
R5
Resistance
5.1kΩ
R3
Resistance
10kΩ
C18
Capacitance
47uF
TP8
L1
Inductance
6.8uH
C11
Capacitance
39pF
R21
Resistance
4.7kΩ
C17
Capacitance
100nF
R10
Resistance
10kΩ
C5
Capacitance
10uF
TP3
TP1
C16
Capacitance
22uF
R4
Resistance
10kΩ
C1
Capacitance
100nF
R32
Resistance
680Ω
R6
Resistance
5.1kΩ
C14
Capacitance
10uF
Q2
C15
Capacitance
22uF
R31
Resistance
120Ω
R14
Resistance
23.7kΩ
R11
Resistance
1.91kΩ
R22
Resistance
33Ω
R19
Resistance
51.1kΩ
C12
Capacitance
100nF
C10
Capacitance
4.7nF
C7
Capacitance
33uF
TP2
R17
Resistance
5kΩ
R28
Resistance
100Ω
R33
Resistance
680Ω
R27
Resistance
100Ω
R2
Resistance
10kΩ
TP4
R24
Resistance
100Ω
D5
J5
J4
J7
F1
J3
SW1
SW2
D2
J6
F2
D4
J8
U4
J2
Project Specification
Project Overview
Status: Approved for schematic development
A custom VEX U localization coprocessor for Prism Robotics. An ESP32-WROOM-32E gathers four VL53L1X ToF channels and one LSM6DS3 IMU over I2C, computes localization data, and exchanges data with a VEX V5 Brain over an RS485 link.
Intended Use
Robot-mounted prototype operating from the VEX smart-cable 12 V supply, with USB-C available for programming, debugging, and alternate bench power.
What the Device Should Do
  • Power safely from VEX 12 V, USB-C 5 V, or both simultaneously.
  • Prevent backfeeding between the VEX Brain and USB host.
  • Program and monitor the ESP32 through onboard USB-to-UART.
  • Connect four ToF breakout boards and one IMU breakout.
  • Communicate bidirectionally with the VEX V5 Brain through RS485.
  • Tolerate common wiring errors without damaging the VEX Brain, USB port, or ESP32.
Main Features
  • ESP32-WROOM-32E bare module.
  • Four 1x06 ToF ports with shared I2C/interrupt and individual XSHUT controls.
  • One 1x12 IMU breakout header.
  • USB-C USB 2.0 device port and CP2102N bridge with automatic boot/reset.
  • RJ9/4P4C VEX interface carrying 12 V, GND, and RS485 A/B.
  • Protected dual-source power path.
System Architecture

Diagram


VEX RJ9: node_12V + RS485 12V input protection 12V to node_5V buck USB-C VBUS + D+/D- USB fuse and ESD protection Automatic isolated node_5V power path 5V to 3.3V regulator ESP32-WROOM-32E CP2102N USB-UART Shared I2C bus 4x VL53L1X breakout ports LSM6DS3 breakout port MAX485-compatible breakout header
Hardware Subsystems
Protected Power
  • RJ9 12 V input: fuse/current limiting, reverse-polarity protection, surge/TVS clamp, and filtering before a documented buck regulator.
  • USB-C VBUS: independent fuse/current limiting and 5 V TVS protection.
  • Automatic power-path isolation must prevent either 5 V source from driving the other.
  • 5 V to 3.3 V regulation nominally uses AMS1117-3.3 with 10 uF input and 10 uF + 0.1 uF output capacitors. Thermal suitability must be checked against the final load; substitute a higher-efficiency 3.3 V regulator if required to protect the ESP32 and maintain reliable operation.
  • Add accessible test points for 12V_PROTECTED, 5V_SYS, 3V3, and GND.
ESP32 Core
  • ESP32-WROOM-32E module with all supply/ground pins connected.
  • EN: 10 k pull-up and 1 uF to GND.
  • IO0: 10 k pull-up.
  • Manual BOOT and RESET access is desirable in addition to automatic reset.
  • Preserve antenna keepout for the PCB layout phase.
USB Programming
  • USB-C USB 2.0 receptacle, 5.1 k CC1/CC2 pull-downs.
  • Low-capacitance ESD protection on D+/D- and protected VBUS.
  • CP2102N with datasheet-required 0.1 uF and 4.7 uF decoupling.
  • CP2102N TX -> ESP32 IO3/RX0; CP2102N RX -> ESP32 IO1/TX0.
  • DTR/RTS drive a verified two-transistor 2N3904 automatic boot/reset network.
Sensor Interfaces
  • Shared SDA = IO21 and SCL = IO22, with one board-level pair of pull-ups sized for the bus and breakout pull-ups.
  • Shared TOF_INT = IO19.
  • XSHUT1..4 = IO12, IO13, IO14, IO15.
  • IMU_INT = IO18.
  • External connector signals receive ESD protection and conservative series resistance where compatible.
  • GPIO12 is an ESP32 strapping pin; the connected ToF breakout must not pull it high during reset.
VEX RS485 Interface
  • ESP32 UART2 RX = IO16 and TX = IO17.
  • 1x07 breakout header carries 3V3, GND, TX, RX, combined direction control if required, A, and B.
  • RJ9 middle pins carry RS485 A/B; outer pins carry 12 V and GND.
  • Add RS485-side ESD/surge protection and optional/fitted-as-required termination/biasing.
  • Verify the selected breakout is truly 3.3 V compatible; classic MAX485 ICs are normally 5 V devices.
Interfaces and Connections

Table


InterfaceNets / GPIONotes
I2CIO21 SDA, IO22 SCLShared by all sensor ports
ToF interruptIO19Shared
ToF shutdownIO12/13/14/15One per port; IO12 boot-state risk
IMU interruptIO18Dedicated
USB UART0IO3 RX0, IO1 TX0Cross-connected to CP2102N
RS485 UART2IO16 RX2, IO17 TX2Through breakout header
VEX cableRJ9 12 V, GND, A, BExact mating pin orientation must be verified before layout
Power and Runtime Expectations
No battery. The design operates from VEX 12 V or USB-C 5 V. USB-only operation must respect the current advertised by the USB source; no assumption of USB-PD is allowed.
Power Tree and Power Budget

Table


RailEstimated continuousDesign peakMain loads
3V3250-400 mA750 mAESP32, CP2102N, sensor breakouts, RS485 breakout
5V_SYS300 mA typical850 mA3V3 regulator input plus margin
12V VEX input~150 mA typical450 mA design limitReflected 5 V load through buck
Regulators, protection devices, inductors, connectors, and power-path parts must be sized from verified datasheet loads with at least 25% practical margin. USB operation may need firmware to avoid sustained radio/current peaks when attached to a current-limited host.
Manufacturing and Assembly Expectations
Prototype-intent SMD design using widely available components. Use documented footprints and manufacturer-recommended land patterns. Provide test points on power rails and critical programming/interface signals.
Firmware-Relevant Hardware Requirements
  • ESP32 UART bootloader through CP2102N with automatic DTR/RTS reset.
  • I2C startup sequence must hold all ToF XSHUT lines low, then enable and re-address sensors individually.
  • Firmware must account for GPIO12 strapping constraints.
  • UART2 protocol and RS485 direction control depend on the selected breakout implementation.
Physical Design Expectations
Robot-mounted board. USB-C and RJ9 must be mechanically accessible. ESP32 antenna must sit at a board edge with a copper/component keepout. Sensor ports should be clearly keyed/labeled to reduce wiring mistakes.
Important Design Decisions
  • VEX 12 V is converted onboard to 5 V.
  • USB and VEX-derived 5 V support simultaneous connection using automatic backfeed protection.
  • Protection of the VEX Brain, USB source, and ESP32 takes priority over minimum BOM cost.
  • Sensor boards and RS485 are connected through breakout headers rather than integrated sensors/transceiver.
Assumptions
  • VEX RJ9 outer-pin polarity and A/B orientation will be verified against the actual cable/Brain before PCB layout.
  • Sensor breakout boards operate from 3.3 V and expose 3.3 V logic.
  • The RS485 breakout exposes a usable direction-control arrangement within seven header pins.
  • Exact board dimensions and connector positions are deferred to PCB layout.
Change Notes
  • Initial specification created from the supplied design brief.
  • Added onboard 12 V-to-5 V conversion, dual-source power-path isolation, comprehensive connector/power protection, and a required bring-up/test plan.
  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Protected Power

  • ESP32 Core

  • USB Programming

  • Sensor Interfaces

  • VEX RS485 Interface

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes