Tophat-Razr PCB Design Overview
PROJECT: Tophat-Razr-v1
BOARD VERSION: v6
OVERVIEW:
Custom 4-layer PCB for a handheld Linux terminal device called
Tophat. The board fits inside the lower half of a Motorola RAZR
V3m clamshell shell. The device runs Alpine Linux with fish shell
as default, an IPFS lite node for peer-to-peer package
distribution, and SSH. Packages are distributed via IPFS with a
three-tier signed index system (Tier 0 backtested signed release,
Tier 1 IPFS p2p mirror, Tier 2 opt-in community overlay).
BOARD SPECIFICATIONS:
- Dimensions: 88mm x 50mm (confirm with calipers from donor phone)
- Stackup: 4-layer, 0.8mm total thickness
- Copper: 1oz all layers
- Finish: ENIG (gold) — required for fine pitch QFN pads
- Solder mask: green
- Layer 1 top: components, signal traces, RGB parallel lines
- Layer 2: unbroken ground plane — no slots or breaks between chips
- Layer 3: power planes — 5V, 3.3V, 1.8V pours
- Layer 4 bottom: SPI buses, keyboard matrix, USB diff pairs
- Manufacturer: JLCPCB, 5 bare boards + 2 PCBA assembled
THREE COMPUTE CHIPS:
-
Allwinner V3s (QFN-88, 10x10mm, 0.4mm pitch) LCSC: C89764
- Main CPU — Alpine Linux anchor, fish shell, IPFS lite node
- RGB parallel display output to main display via hinge flex
- SPI0 master → RK3528 (task offload)
- SPI1 master → ESP32-S3-WROOM-1 (network + keypress)
- I2S audio → MAX98357A speaker amp
- UART0 debug (test points only, no connector)
- Boots from SPI NOR flash 16MB on SPI bus
- 33 ohm series resistor on all SPI CLK lines
- 100nF decoupling cap on every power pin, placed <1mm from pin
-
Rockchip RK3528 (LFBGA-450, 0.65mm pitch)
- Burst compute — sleeps <1mA idle, wakes on demand from V3s
- SPI0 slave ← V3s
- WAKE GPIO output → V3s (RK3528 signals ready to receive)
- READY GPIO output → V3s (RK3528 signals task complete)
- Powers down aggressively between burst tasks
- Requires careful BGA escape routing — if 4-layer insufficient upgrade to 6-layer 1.0mm stackup
- Power rails: 3.3V, 1.8V, 1.0V from AXP203
-
ESP32-S3-WROOM-1 MODULE (18x25.5mm) LCSC: C2913202
- WiFi 4 + Bluetooth 5 — module handles all RF, no external antenna components needed
- Placement: top right corner, antenna end overhanging board edge or facing shell exterior
- NO copper pour under antenna section of module
- Keyboard matrix scanner: 4 rows x 4 columns GPIO
- Native USB-C OTG interface (D+/D- to USB-C port)
- I2C master → FUSB302 USB-C PD controller
- SPI1 slave ← V3s (network packets + keypress events)
- WAKE GPIO output → V3s (pulls high on keypress or network)
- DATA_READY GPIO output → V3s (signals data waiting on SPI)
- Cover display driver → ST7789 1.3in via SPI
- Runs independently while V3s sleeps
POWER MANAGEMENT:
AXP203 PMIC (QFN-48, 6x6mm, 0.5mm pitch)
LCSC: C88659
- Single power management IC — handles everything
- Input: 5V from USB-C VBUS via FUSB302
- LiPo charge: internal charger, max 1A charge rate
- Power rails output:
- 3.3V → V3s, ESP32-S3, display, audio, flash, SD
- 1.8V → V3s IO, RK3528 IO
- 1.0V → RK3528 core
- I2C slave ← ESP32-S3 (receives charge current commands)
- Battery gauge built in
- NO BQ25895 — AXP203 internal charging only
FUSB302BUCX USB-C PD Controller (QFN-24, 3x3mm, 0.5mm pitch)
LCSC: C442699
- Negotiates USB-C PD up to 20V/3A (60W)
- CC1/CC2 from USB-C port
- I2C → ESP32-S3 (reports negotiated voltage/current)
- ESP32-S3 commands AXP203 charge current accordingly
- Falls back to 5V/500mA standard charge if no PD adapter
LiPo Cell:
- 800mAh, approximately 50x40x4mm
- JST-PH 2-pin connector
- Sits alongside chips within 8mm depth budget
- Placement: bottom right zone of board
INTER-CHIP SPI BRIDGE:
V3s SPI0 ↔ RK3528:
- Up to 40Mbps
- Signals: CLK, MOSI, MISO, CS
- 33 ohm series on CLK
- WAKE + READY GPIO handshake
- Purpose: burst task offload (heavy IPFS sync, compile)
V3s SPI1 ↔ ESP32-S3-WROOM-1:
- Up to 40Mbps
- Signals: CLK, MOSI, MISO, CS
- 33 ohm series on CLK
- WAKE + DATA_READY GPIO handshake
- Purpose: network packets, keypress events, power commands
Simple frame protocol:
- [1 byte type][1 byte length][N bytes payload]
- 0x01 = keypress (2 bytes: keycode + modifier)
- 0x02 = network packet (up to 1500 bytes raw ethernet frame)
- 0x03 = power command (1 byte)
- 0x04 = ack
All SPI traces: layer 4, parallel routing, matched length,
under 30mm total, 33 ohm series termination on CLK lines.
Shared ground plane layer 2 unbroken between all three chips.
DISPLAY:
Main display — ILI9341 2.4in TFT
- Interface: RGB parallel from V3s
- Connector: 24-pin FPC, 0.5mm pitch
- Placement: top edge left of board
- Connects via hinge flex cable to display in top shell half
- RGB lines: length matched on layer 1
Cover display — ST7789 1.3in TFT
- Interface: SPI from ESP32-S3
- Connector: 12-pin FPC, 0.5mm pitch
- Placement: top edge right of board
- Shows IPFS node status, peer count, cache health, battery when main display off
Hinge flex connector:
- Centre top edge of board
- Carries: RGB parallel signals + I2S audio to top shell half
- Flex cable routes through original V3m hinge
AUDIO:
MAX98357AEWL I2S amplifier (WLCSP-9)
LCSC: C460459
- I2S signals from V3s
- Drives original V3m speaker
- Placement: near hinge flex connector
SPH0645LM4H MEMS microphone
LCSC: C460782
- PDM interface to V3s
- Placement: near original V3m microphone aperture in shell
STORAGE:
SPI NOR Flash 16MB (SOP-8)
LCSC: C97521
- Connected to V3s SPI bus
- Boot source for Alpine Linux + V3s U-Boot
- Placement: close to V3s
microSD slot
LCSC: C91145
- Connected to V3s SDMMC interface
- User data, IPFS package cache, additional storage
- Placement: right edge of board, accessible via shell cutout
USB-C:
GCT USB4135-GF-A receptacle
LCSC: C165948
- Placement: bottom left edge (replaces original mini-USB cutout in V3m shell)
- VBUS → AXP203 charge input
- D+/D- → ESP32-S3 native USB OTG
- CC1/CC2 → FUSB302 PD controller
- USB D+/D- differential pair: 90 ohm impedance, layer 4
KEYBOARD MATRIX:
- 4 rows x 4 columns = 16 keys
- Maps to V3m numeric keypad (12 keys) + *, #, D-pad centre, call/end softkeys
- BAT54S Schottky diodes on each column (ghosting prevention) LCSC: C15757
- 10k pull-down resistors on each row
- GPIO from ESP32-S3
- Matrix traces run full width of bottom edge of board
- Route directly to V3m key contact pad locations
NUMLOCK-STYLE KEY MAPPING (software, on ESP32-S3):
- 1-9, 0 → T9 multi-tap for letters
-
- → Ctrl modifier
- → Space / Enter
- D-pad up/down → terminal history scroll
- D-pad left/right → cursor movement
- Softkey left → Tab
- Softkey right → Escape
- Long press any number → symbol (!@#$%^&*())
PASSIVES AND SUPPORTING COMPONENTS:
- 100nF 0402 decoupling caps x20 (LCSC: C14663) Place <1mm from every power pin on every chip
- 10uF 0402 bulk caps x6 (LCSC: C19702) Place at power entry to each chip zone
- 4.7uH 0402 inductors x2 (LCSC: C1035) For AXP203 buck converter outputs
- 10k 0402 resistors x16 (LCSC: C25744) Keyboard matrix row pull-downs
- 33 ohm 0402 resistors x8 (LCSC: C25082) SPI CLK series termination (2 per SPI bus x 4 signals)
- BAT54S diodes x16 (LCSC: C15757) Keyboard matrix column ghosting prevention
- ESD protection PRTR5V0U2X x3 (LCSC: C12333) On USB-C lines, display lines, SPI lines
- LED 0402 red x1 (LCSC: C72043) Charge status indicator
- Tactile reset switch x1 (LCSC: C318884) Hidden inside shell, accessible via pinhole
CONNECTORS PLACEMENT SUMMARY:
- Top edge left: 24-pin FPC 0.5mm (main display)
- Top edge centre: hinge flex connector (RGB + audio)
- Top edge right: 12-pin FPC 0.5mm (cover display)
- Right edge: microSD slot
- Bottom left edge: USB-C receptacle
- Bottom right: JST-PH 2-pin LiPo connector
- Corner (any accessible): 4x debug test points (GND, 3V3, UART0_TX, UART0_RX)
CRITICAL ROUTING RULES:
- Ground plane layer 2: completely unbroken between all chips
- RGB parallel lines: length matched ±0.15mm, layer 1
- USB D+/D-: 90 ohm differential, layer 4
- SPI CLK lines: 33 ohm series termination resistor on each
- SPI buses: all 4 signals parallel routed, matched length, layer 4, under 30mm
- Decoupling caps: 100nF on every power pin <1mm from pin
- No copper pour under ESP32-S3-WROOM-1 antenna section
- LiPo and power components: bottom right zone only
- Keyboard matrix traces: bottom edge, layer 4
- BGA escape (RK3528): single via escape, 0.1mm trace/space If insufficient → upgrade to 6-layer 1.0mm
POWER BUDGET TARGETS:
- Deep idle (ESP32 watching, rest asleep): ~45mA / 0.225W
- Terminal active (V3s + ESP32): ~200mA / 1W
- Burst compute (all three chips): ~600mA / 3W
- Target runtime: 4+ hours typical use on 800mAh LiPo
IPFS PACKAGE DISTRIBUTION SYSTEM:
- Three tier signed package index
- Tier 0: backtested signed release (primary key, offline signing)
- Tier 1: same packages mirrored over IPFS p2p (CID-based fetch)
- Tier 2: community overlay (separate key, opt-in)
- Each package: {name, version, sha256, cid, tier, signature}
- Client verifies signed index → fetches by CID → sha256 verify
- Node collection digest: sha256 of sorted cid:sha256 pairs
- Nodes with failed integrity checks stop seeding automatically
- DHT-based peer discovery, no central server
- Bootstrap peers hardcoded in app config
- IPNS pointer for index resolution
SOFTWARE STACK:
- Bootloader: U-Boot for V3s
- OS: Alpine Linux minimal (musl libc)
- Shell: fish (default, pre-configured)
- Package manager: apk pointing at Tophat IPFS repo
- Prompt: Starship or custom fish prompt
- Default tools: fzf, zoxide, ssh, git, curl
- Bridge daemon: tophat-bridge (C, userspace SPI handler) Routes SPI frames to /dev/uinput (keyboard) or TUN/TAP interface (network)
- IPFS: kubo-lite or go-ipfs-lite node
- Cover display daemon: reads IPFS node stats, peer count, battery, pushes to ST7789 via ESP32-S3
Thought for 1 sec
I can’t continue executing project setup right now because this account has no available ACUs, so AI design actions are unavailable.
So far in this session, no schematic/layout changes were made. You provided a detailed v6 specification for Tophat-Razr-v1, a 4-layer handheld Linux terminal PCB targeting the Motorola RAZR V3m shell, with V3s + RK3528 + ESP32-S3 compute, AXP203 power management, USB-C PD, displays, audio, storage, keyboard matrix, and routing/placement constraints.
Remaining work once ACUs are available:
- Rename the project from the random placeholder to Tophat-Razr-v1 and update the description.
- Create a persistent project specification document from your v6 requirements.
- Validate the architecture, especially RK3528 BGA feasibility on 4 layers and AXP203 rail/current suitability.
- Build the schematic in functional blocks: power, compute, USB-C/PD, displays, audio, storage, keyboard, debug.
- Create power budget, bring-up, firmware, and regulatory notes.
- Move into PCB setup: 88 mm × 50 mm, 4-layer 0.8 mm stackup, placement constraints, then routing rules.
Create spec document
Check BGA feasibility
Review power budget
Plan schematic blocks
No schematic yet
Talk to Flux to get started.
