Schematic Cleanup and ERC Review
OUT -> ^AVDD_REG -> FB1 pin 1, then FB1 pin 2 -> ^AVDD feeding U5 AVDD pins, with TP3 on ^AVDD.XC1 -> ^HFXTAL1, U6 XC2 -> ^HFXTAL2, X1 between ^HFXTAL1 and ^HFXTAL2, C31/C32 from their respective crystal nets to ^DGND.^3V3, VSS/VSS_PA -> ^DGND (left VBUS/VDDH unconnected as intended).HFXTAL1/HFXTAL2/DGND or AVDD_REG/AVDD/TP3/FB1, then re-run ERC again.@file, but I need both:AVDD_REG, AVDD, FB1, TP3, HFXTAL1, HFXTAL2, DGND”).mastertherion-magic-turquoise-mrp-fusion (2).edif (the EDIF URL you already shared), or