• Portable prototype and validation platform for short-range 315 MHz transmit/receive experiments.
• Installed inside a non-conductive enclosure with the main PCB, LiPo battery, remote USB connector, OLED, controls, and bulkhead antenna.
• Powered from a protected 1S LiPo during normal use and from 5 V USB for charging, programming, and operation.
• Not yet a production-released or regulatory-approved design.

• Run application firmware on the ESP32-S3-WROOM-1-N16R8.
• Transmit and receive at 315 MHz through the CC1101 and external 50 ohm antenna path.
• Charge a connected protected 1S LiPo from USB at approximately 200 mA.
• Operate from USB or battery without backfeeding either source.
• Maintain a regulated 3.3 V rail as the battery moves through its usable voltage range.
• Support native USB programming and recovery using remote BOOT and RESET controls.
• Drive a remote I2C OLED and read one remote user control.
• Measure battery voltage using an ESP32 ADC input.

• ESP32-S3 module with 16 MB flash and 8 MB PSRAM.
• CC1101 315 MHz transceiver with 26 MHz reference crystal and TI-derived RF matching network.
• U.FL RF output for an internal coax pigtail to an enclosure-mounted SMA female connector.
• TP4056 LiPo charger set to approximately 200 mA.
• AN1149-style USB/battery load sharing using a P-channel MOSFET and Schottky diode.
• TPS63070 synchronous buck-boost regulator generating 3.3 V.
• Remote USB, OLED, and control connectors.
• Native USB ESD protection and 22 ohm series termination footprints.
• Battery ADC divider with RC filtering.

Diagram

• U1: ESP32-S3-WROOM-1-N16R8.
• Native USB uses GPIO19 for D- and GPIO20 for D+.
• USB data path includes USBLC6-2SC6 ESD protection and 22 ohm series resistors.
• EN and GPIO0 must support reliable reset, bootloader entry, and recovery through the remote controls connector.
• The ESP32 module PCB antenna must be placed at a board edge with the manufacturer-required all-layer keepout. Battery, cables, copper, screws, bosses, and other hardware must remain outside this region.

• U2: CC1101RGP configured for 315 MHz operation.
• Y1: 26 MHz reference crystal with the implemented load network.
• Retain the complete TI-derived differential-to-single-ended balun, matching, and low-pass network.
• SPI assignments:

• RF output must transition to a 50 ohm controlled-impedance trace and terminate at J5, Hirose U.FL-R-SMT-1(10).

• J1: JST-PH battery connector for a protected 1S LiPo.
• U4: TP4056 linear charger configured for approximately 200 mA charge current.
• USB/battery source sharing follows the Microchip AN1149 approach using Q1 SI2309 and D1 B5819W-SL.
• The circuit must prevent USB-to-battery and battery-to-USB backfeed while allowing the system to operate during charging.
• Charging thermal performance must be checked at the maximum expected USB input voltage and battery state.

• U3: TPS63070 synchronous buck-boost regulator.
• Nominal output: 3.3 V.
• Must support at least 600 mA output at 3.0 V battery input, including ESP32 radio-current transients and CC1101 activity.
• Input/output capacitors, inductor saturation current, feedback routing, and power-ground layout must follow the device datasheet.

• J3 OLED connector: 3V3, GND, I2C_SDA GPIO8, I2C_SCL GPIO18.
• J4 controls connector: GND, BOOT GPIO0, RESET/EN, USER GPIO1.
• J3 and J4 use compact 1.25 mm four-position connectors.
• I2C pull-ups are 4.7 kohm to 3.3 V unless revised after cable-length testing.
• The OLED module and all buttons/switches are mechanically off-board and cabled. Only J3/J4 headers belong on the main PCB.
• Remote buttons shall connect each active-low control signal (BOOT and EN) to GND at the remote panel; USER behavior is firmware-defined and must not be left floating in firmware.

• Battery voltage is measured on GPIO4 through a high-value divider and RC filter.
• Firmware must use the populated resistor ratio and ADC calibration to calculate battery voltage.
• The divider must not expose the ADC pin above its allowed input range at maximum LiPo voltage.

• Battery: protected 1S LiPo, nominal 3.7 V, assumed usable range approximately 3.0 V to 4.2 V subject to the selected cell protection limits.
• USB input: nominal 5 V through the remote USB harness.
• Charge current: approximately 200 mA.
• Runtime is not yet specified because battery capacity and firmware duty cycle are not defined.
• Firmware should support light-sleep or deep-sleep operation where practical and disable unnecessary radio activity between events.
• The design must tolerate short ESP32-S3 transmit-current peaks without resetting or pulling the 3.3 V rail out of regulation.

Diagram

• The regulator requirement remains at least 600 mA at 3.0 V input, leaving about 33 mA above the 567.4 mA design peak.
• Worst-case battery input current is approximately 0.734 A using 3.3 V output, 3.0 V input, and 85% efficiency. Size the protected cell and complete power path for at least 1 A peak with margin.
• Full 200 mA charging plus the system design peak requires about 0.616 A from 5 V USB, which exceeds a standard 500 mA USB 2.0 source. Firmware must reduce peak activity or charge current unless the source capability is explicitly higher.
• TP4056 dissipation is about 0.40 W at 5.0 V USB/3.0 V battery and 0.45 W at 5.25 V/3.0 V; exposed-pad thermal copper is required and thermal regulation may reduce charge current.
• Sleep planning is about 0.22–0.50 mA before unknown OLED leakage. Runtime remains parametric because battery capacity, OLED model/current, and firmware duty cycle are unspecified. See the dedicated Power Budget project file.

• Four-layer PCB, nominal 1.6 mm finished thickness.
• Layer intent: Top signal/components; Inner 1 uninterrupted GND; Inner 2 power distribution; Bottom signal/passives.
• Production footprints and MPN metadata are required for all fitted parts.
• RF matching components must use the intended small RF packages and be placed according to the CC1101 reference layout principles.
• Controlled-impedance fabrication notes are required for 50 ohm RF and 90 ohm USB differential routing.
• Avoid substitutions in the RF network, regulator inductor, crystal, USB ESD device, module, and connectors without engineering review.
• Bulky loop test points are excluded; use accessible SMT pads or compact test pads only where bring-up requires them.
• Mechanical/DNI BOM item: U.FL/MHF1 plug to SMA-female bulkhead pigtail, 100 mm to 150 mm, RG178 or 1.13 mm 50 ohm coax, with bulkhead nut and washer.

• Native USB firmware download and serial/JTAG support as permitted by the ESP32-S3 implementation.
• GPIO0 BOOT and EN reset controls must remain usable when the board is enclosed.
• Initialize GPIO assignments exactly as listed in this specification.
• Battery ADC firmware must account for divider ratio, attenuation setting, calibration, and filtering.
• CC1101 firmware must support 315 MHz configuration and expose GDO0 for packet/status interrupts.
• I2C firmware must use GPIO8 SDA and GPIO18 SCL at 3.3 V logic.
• Firmware updates must remain possible through the remote USB interface without opening the enclosure, assuming remote BOOT/RESET controls are accessible.

• Main PCB is a single enlarged Standard 4 Layer board. Final placement-review outline is recorded from the PCB after optimization; board growth is permitted to maintain routing corridors.
• The USB-C receptacle, OLED, and buttons are mechanically off-board/cabled. The main PCB carries only J2/J3/J4 wired interfaces; do not fit those panel devices directly to the main PCB.
• The remote USB-C receptacle subassembly must provide independent 5.1 kohm Rd resistors from CC1 and CC2 to GND locally at the receptacle (unless a verified Type-C sink controller is used). CC conductors do not need to traverse J2. VBUS draw must respect the source advertisement; no USB-PD controller is present.
• Prefer one main board. A second small panel board is allowed only for the remote USB-C receptacle and local CC/ESD mechanics, or for the OLED/buttons, when the enclosure requires it; connection remains by cable to J2/J3/J4.
• Preserve generous routing corridors between the power, MCU, and RF blocks and at every cabled edge header.
• Up to four 2.2 mm NPTH mounting holes may be retained only where mechanically useful. Hole centers should be at least 2.5 mm to 3.0 mm from board edges and must not violate antenna or copper clearances.
• The ESP32 PCB antenna may remain inside an ordinary non-conductive plastic enclosure. Preserve an air gap and keep copper, battery, wiring, screws, bosses, and conductive or filled plastics out of the antenna region.
• Place the ESP32-S3-WROOM-1 antenna end at a board edge with approximately 5 mm overhang/keepout intent and enforce the Espressif all-layer antenna keepout in final copper/routing.
• The SMA female connector mounts through the enclosure, not on the PCB edge.
• Route the internal coax without sharp bends and without applying mechanical load to J5.
• Remote USB data must remain on a USB-capable cable/interconnect; do not substitute a generic untwisted harness for D+ and D-. The off-board receptacle/panel assembly must include CC1/CC2 sink resistors and document cable pinout before manufacture.
• Connector access, cable bend radius, battery placement, and enclosure fasteners must be verified in the mechanical assembly before release.

• Use a discrete CC1101 RF section rather than a pre-certified 315 MHz module.
• Use U.FL on the PCB and an internal coax pigtail to the enclosure SMA connector instead of a board-edge SMA.
• Retain Molex 5055780621 for the remote USB interface because no verified compact locking six-position replacement was available in the library.
• Omit the 1 x 6 service header; use native USB plus remote BOOT and RESET.
• Use a 3.3 V buck-boost supply rather than an LDO so the full useful 1S LiPo range can be used.
• Limit charging to approximately 200 mA to reduce thermal load and suit a compact enclosure.

• The selected LiPo is protected and can safely supply at least 1 A peak.
• Exact battery capacity, runtime target, OLED model/current, USB cable length, enclosure material, antenna model, and desired 315 MHz range are not yet specified.
• USB-C source-current advertisement, LiPo capacity/C-rating/protection trip limits, and exact remote USB-C receptacle/panel circuit remain open release inputs.
• Regional legality, allowed frequency, transmit power, duty cycle, and certification requirements must be confirmed for the deployment country and application.
• The remote USB connector pin numbering and cable assembly must be documented before harness fabrication.
• Final controlled-impedance trace widths depend on the PCB fabricator's actual four-layer stackup.

• All intended pins connected or explicitly marked no-connect.
• Power, ground, decoupling, boot straps, regulator support circuitry, charging circuitry, and RF network match the applicable datasheets/reference designs.
• ERC has no unresolved critical errors; justified warnings are documented.

• All 56 components are within the 70 mm x 27 mm outline and have valid production footprints.
• ESP32 antenna all-layer keepout is clear of copper, components, battery, cables, and mechanical hardware.
• CC1101 matching network is compact and follows reference-layout signal flow with an uninterrupted RF return path.
• RF_50OHM is routed as 50 ohm controlled impedance; USB D+/D- are routed as a 90 ohm differential pair using the selected fab stackup.
• Switching-regulator high-current loops are minimized and feedback routing is kept away from the switch node.
• No unrouted airwires, dangling traces, or unresolved critical DRC violations remain before manufacturing export.

• No short between VBUS, BAT, SYS, 3V3, and GND before power-up.
• Charger current is approximately 200 mA and load sharing shows no prohibited backfeed.
• 3.3 V remains within operating tolerance from 3.0 V to 4.2 V battery input under representative peak load.
• ESP32 enumerates and programs over the remote USB assembly.
• BOOT, RESET/EN, USER, OLED, battery ADC, CC1101 SPI/GDO0, and 315 MHz RF path pass functional tests.

• Reorganized the specification into behavior, architecture, subsystem, interface, power, manufacturing, firmware, physical, and acceptance sections.
• Added project-stage status and documented the current 88-airwire routing state.
• Added architecture and power-tree diagrams.
• Added a preliminary peak-current budget and worst-case battery-input estimate.
• Clarified enclosure antenna rules, USB interconnect requirements, unresolved assumptions, and measurable validation criteria.