ESP32 Sensor and Control Schematic
Thought
Work done
- Applied the required explicit per-net trace-width rules: 12V and HEATER_12V_SW at 2.0mm, GND at 1.0mm with Bottom preference, 3V3/5V at 0.8mm, and remaining named signal/control nets at 0.3mm.
- Reconfirmed the PCB is on a 120mm × 100mm, Standard 2-layer stackup.
- Reworked placement once to improve separation and keep the high-current zone on the right; relay/J1/J2 remain intended for the right-side power/heater area.
- Fixed the Layers with Multiple Fills issue by limiting unintended sublayout fill participation; latest review shows that category is now clean.
- ✅ Net-specific trace-width rules applied and verified for the listed power/signal nets.
- ✅ Bottom-layer GND fill conflict improved: Layers with Multiple Fills is now clean.
- ❌ Routing is not complete: latest review still reports 24 airwires.
- ❌ DRC is not clean: latest review still reports 15 overlapping copper errors and 24 airwire errors.
- ❌ Final fabrication-ready state could not be confirmed: not at 0 airwires / 0 DRC errors.
- Continue with the fix-verify loop: resolve the remaining U5/TFT and 46116ccf copper overlaps, then route all nets in phases — high-current 12V/heater first, then 5V/3V3/GND, then SPI/control/sensor signals — and rerun DRC until clean.
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NSS Heater Implementation Status
Completed
- Project renamed and description updated for the NSS Heater thesis design.
- Schematic connectivity revised to match required ESP32 GPIO mapping:
- DS18B20 patient sensor: GPIO4 with 4.7k pull-up to 3V3.
- DS18B20 NSS sensor: GPIO15 with 4.7k pull-up to 3V3.
- Relay control: GPIO26.
- ILI9341 SPI: SCK GPIO14, MOSI GPIO13, MISO GPIO12, CS GPIO5, DC GPIO21, RST GPIO22, VCC/BL to 3V3.
- Buzzer: GPIO25.
- LED: GPIO2 through 220 ohm resistor.
- Push button: GPIO18 to GND for firmware INPUT_PULLUP.
- Added 1N4007 flyback diode across the relay supply path.
- Configured terminal blocks J1 for 12V input and J2 for heater output.
- PCB resized to 120mm x 100mm and set to a 2-layer stackup.
- Layout rules applied:
- Default: 0.254mm trace/clearance.
- GND: 1.0mm trace, 0.3mm clearance.
- 3V3/5V: 0.8mm trace, 0.3mm clearance.
- 12V/heater: 2.0mm trace, 0.5mm clearance, 1.0mm via / 0.6mm drill intent.
- SPI/display nets: 0.3mm trace, 0.254mm clearance.
- Component placement segregated logic/UI/sensors to the left and heater/12V circuitry to the right.
Remaining items
- Physical routing is not complete; airwire checks still report unrouted connections.
- Existing copper overlap issues remain in the layout and need PCB-editing cleanup before fabrication.
- The schematic currently uses a relay-module style symbol rather than a fully discrete SRD-05VDC-SL-C relay plus transistor driver.
- Final fabrication readiness requires routing completion and a clean DRC/ERC pass.
Completed
Remaining items
