Phase 1 Board Design Specifications
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Toob-Boot HIL-Rig — Phase‑1 Board Specification
Scope
Phase 1 implements only:
- SCC — Site-Carrier-Card: one per DUT site.
- BKP — Backplane: passive 5 V/GND/SYNC/SAFE/Slot-ID distribution for N≥8, initially usable for 5 sites and electrically prepared for 8 slots.
- ADP interface definition: passive DUT adapters/harnesses mating to the standardized J-DUT connector.
Phase 2 boards (SNF, DCC-*, RFI) are not designed in this project. Their interfaces are frozen only via SCC DNP reservations and DUT-side connector definitions.
Frozen Interfaces
J-DUT — standard DUT connector, 21 logical pins
1 VDD_BOARD_IN, 2 VDD_MCU_DIRECT, 3 VDD_SENSE, 4 GND, 5 GND, 6 GND_SENSE, 7 UART_TX_TAP, 8 UART_RX reserved, 9 TRIG_GPIO, 10 PHASE0, 11 PHASE1, 12 RECOVERY open-drain, 13 SWDIO, 14 SWCLK, 15 nRESET, 16 JTAG_TCK, 17 JTAG_TMS, 18 JTAG_TDI, 19 JTAG_TDO, 20 SPARE0, 21 SPARE1.
The schematic uses a keyed/latching higher-position connector candidate (
J_DUT_FINAL) so the frozen 21 logical contacts are preserved and extra contacts can remain reserve/NC.J-BP — SCC/backplane slot connector
Multiple 5 V and GND pins, SYNC, SAFE, SLOT_ID[0..2] for up to 8 slots, and spares/reserves. Slot-ID strapping is implemented for slots 1–8; slots 6–8 are electrically prepared for expansion.
J-SNF / SPI tap reservation
SCC includes DNP reservation for future SNF trigger and high-impedance SPI tap pads. No SNF circuitry is populated or designed in Phase 1.
SCC Functional Blocks
- 5 V input protection: protected 5 V input via resettable PTC/fuse class part, local bulk capacitance and separation between shared input and local switching load.
- Housekeeping 3.3 V rail: LDO from protected 5 V, powering Pico
VSYS, DAC, INA monitor, EEPROM, comparator and sense circuitry. PicoVBUSis intentionally not used for power. - Victim rail: buck-based adjustable supply using
U_VICTIM_BUCK(LMR33630-Q1 class) with inductor, bootstrap, feedback network, DAC feedback injection and power-good monitor. Optional filtering/post-regulation remains a layout/measurement decision to meet the low-noise victim-rail goal. - High-side Kelvin shunt: value/gain to be finalized during calibration, sized for ~1.5 A full-scale design basis.
- Slow monitor: INA-class I2C current/voltage/power monitor.
- Fast monitor: INA187A3-class fast current-sense amplifier to comparator, Pico ADC and test point; optional DNP fast-ADC path remains reserved.
- Load switch: soft-start load switch controlled by Pico, with pull-down OFF and global SAFE design intent.
- Active sink: N-FET + R_lim controlled by Pico PWM/driver, with gate pull-down OFF for safe-state; final sink current and sag waveform calibrated with dummy load.
- OVP/DUT protection: NodeA hard clamp at 3.3 V Zener/TVS class with requirement to keep NodeA ≤3.6 V; DUT signal lines include series/protection topology and unused ESD-array channel is NC.
- Pico socket: RP2040 Pico headers; USB is data-only and backplane-derived housekeeping power feeds the Pico through
VSYS. - Calibration EEPROM: card serial, shunt nominal, sense gain and DUT calibration profile pointer.
- Test points: NodeA, GND_SENSE, fast-sense output, comparator output, trigger lines, sink gate, regulator FB and SYNC.
BKP Functional Blocks
- 5 V PSU input sized for N≥8; target preliminary budget ≥8 A preferred for 8 slots.
- Star-ground distribution: multiple ground pins per slot and a central single-point ground strategy for layout.
- SYNC bus: distributed to all slots; PCB layout must implement short/matched stubs and series termination at the driver.
- SAFE line: host-driven global shutdown request to every SCC.
- Slot-ID strapping: implemented for 8 slots with SLOT_ID[0..2].
- USB is not routed on the backplane.
Preliminary Power Budget
Per SCC preliminary peak design basis:
- Victim rail: up to 1.5 A transient at approximately 0.8–3.6 V.
- Housekeeping 3.3 V: Pico + support ICs, provision 250–300 mA peak until measured.
- 5 V input per card: provision 0.8–1.0 A peak including margins and regulator losses.
- BKP N=8: design target 5 V at ≥8 A preferred; final value confirmed after DUT characterization.
Calibration / Layout-Phase Items
- Final connector P/Ns/footprints for J-DUT, J-BP, J-SNF and Pico socket must be locked against mechanical constraints before PCB layout.
- Victim rail output filtering/post-LDO option must be confirmed by noise and load-step measurements.
- Shunt value, sense gains and comparator thresholds must be calibrated for the actual DUT current envelope.
- Sink FET/R_lim and gate profile must be calibrated against DUT/adapter decoupling.
- Mechanical card size, slot pitch and chassis constraints remain layout inputs.
- Per-DUT ADP pin mapping, injection node and decoupling modifications are adapter-specific, not SCC redesign items.
Layout Constraints to Enforce Later
- Victim power path short, wide, low-inductance: regulator → shunt → switch → NodeA → J-DUT.
- Kelvin force/sense at both shunt and J-DUT.
- Dirty/quiet ground partition with single-point tie near shunt/ADC reference.
- Fast-sense input as tight differential pair away from sink switching edges.
- OVP and ESD protection physically close to NodeA/J-DUT respectively.
- Do not connect USB VBUS into the backplane/SCC power tree; use USB data-only operation for the Pico.
Scope
Frozen Interfaces
J-DUT — standard DUT connector, 21 logical pins
J-BP — SCC/backplane slot connector
J-SNF / SPI tap reservation
SCC Functional Blocks
BKP Functional Blocks
Preliminary Power Budget
Calibration / Layout-Phase Items
Layout Constraints to Enforce Later
