## High-level goal

Implement the hardware from **PDL_REPORT_FINAL.pdf** in Flux EDA: an ESP32-S3 based controller with an SPI TFT (ILI9341), capacitive touch (FT6206), a 16x2 LCD over I2C (via PCF8574 backpack), 4 relay outputs with transistor drivers + flyback diodes, 4 status LEDs, BOOT/RESET buttons, and a 5V power subsystem; then prepare the PCB layout.

## What’s been done so far

- Project metadata updated: description and a “System Architecture” property were added.

- Major components were added and largely wired in schematic:

- **U1** ESP32-S3-DEVKITC-1-N8R2

- **U2** Adafruit ILI9341 SPI TFT module wired to ESP32 SPI + touch header pins (note: not FT6206)

- **U4** PCF8574DWR wired to ESP32 I2C, drives **LCD1** WC1602A (4-bit mode). I2C pull-ups **R1/R2=4.7k** to 3V3.

- **Relays** K1–K4 (SRD-05VDC-SL-C) with **BD139G** drivers Q1–Q4, base resistors **R5–R8=1k**, flyback diodes **D8–D11=1N4007**.

- **LED1–LED4** with 220Ω series resistors.

- **BOOT/RESET** buttons implemented (SW1/SW2) with pulls and EN RC.

- **U3** LM7805CT/NOPB present with input/output caps.

- Fixed a critical schematic bug: relay coil low-side nodes were accidentally shorted into the **EN** net; this was corrected by creating separate nets **RELAY1_COIL_LOW…RELAY4_COIL_LOW**.

- PCB prep started:

- Board outline set to **140mm x 100mm**, **Standard 4-layer** stackup applied.

- Baseline layout rules set (trace width 0.25mm, keepout 0.2mm).

- Review status:

- DRC airwires: failing (board not routed/placed; many airwires).

- ERC: floating pins flagged (expected for unused ESP32 pins, SD pins on TFT module, unused PCF pins, LCD D0–D3 in 4-bit mode, relay L1 pins, and D12 anode).

- FT6206 issue logged: FT6206 not found in library; internal feedback submitted.

## Implementation plan (remaining work only)

1. **Resolve power-input architecture to match the report**: add the intended power input connector (e.g., barrel jack or terminal block) and connect it to the existing **VIN** path; decide and implement reverse-polarity protection using **D12** (currently only cathode tied) or replace with an appropriate solution.

2. **Fix relay output connector wiring**: remove the unintended global **GND** tie on relay output terminal pins; ensure terminals **U5–U8** connect only to the corresponding relay **COM/NO** contact pins (and add NC if required by the report).

3. **Close ERC floating-pin findings intentionally**:

- For **LCD1** D0–D3 (unused in 4-bit mode), mark as NC or leave unconnected intentionally.

- For **PCF8574** unused pins (e.g., P2/P3, ~INT~), either connect ~INT~ to ESP32 (if needed) or label as NC; ensure P2/P3 are not accidentally floating to external nets.

- For **relays K1–K4 L1**, confirm which coil/contact pins should be used and connect/label appropriately.

- For unused **ESP32** pins, label as NC in schematic properties where appropriate.

4. **Reconcile the touch requirement**: modify the design to satisfy **FT6206 capacitive touch**:

- Either add an FT6206 component (human to import/create if library still missing) and wire it to I2C + IRQ + reset per FT6206 reference, or

- Swap U2 to a module/part that actually implements and exposes FT6206 I2C touch, and update connections accordingly.

5. **Verify TFT voltage-domain correctness**: confirm whether the chosen ILI9341 module accepts 5V VCC and 3.3V logic; if not, rewire VCC to 3V3 and add level shifting for SPI/touch signals as needed.

6. **Add missing decoupling/bulk where required by datasheets** (especially around PCF8574, display modules if they expose raw rails, and ESP32 peripheral power pins), and set component properties (value, voltage rating) to match the report.

7. **Prepare PCB layout for placement/routing**:

- Add mounting holes and connector edge-placement decisions.

- Define copper pours/ground fill strategy (continuous GND on an inner layer, antenna keepout for ESP32 dev board/module area).

- Place key connectors at board edges; group power section near input; group relay/terminals away from logic.

8. **Route and clear DRC/airwires**: instruct the user to run Auto-Layout for placement/routing (since manual routing isn’t available here), then re-run **design_rule_check_airwires** and resolve any remaining DRC/erc issues within schematic/connectivity control.

9. **Manufacturability sanity pass**: generate BOM review (availability/MPNs), confirm footprints, and ensure relay contact clearances match intended load voltage (especially if switching mains).