Project Startup


The architecture and power envelope are set. The schematic build is still in progress across the power, ESP32, radio, storage, IR, and protected debug blocks.
Thought for 11 mins 7 sec
Thought for 7 sec
Awaiting 1 background task
Received notification from "ESP32-S3 Toolkit Schematic" that it finished — picking the work back up.
Built the Phase 1 modular proof-of-concept schematic with 156 components and 114 nets, covering ESP32-S3 compute, battery/USB-C power, NFC, sub-GHz, IR, microSD, UI, expansion, and protected debug interfaces. The project was renamed and a Phase 1 Power Budget was created.
Open items
  • Independent ERC/connectivity verification was not completed.
  • Any schematic errors found during review still need remediation.
  • Firmware pin mapping and starter code remain to be generated.
  • PCB layout has not started.
  • Work is paused because no ACUs are currently available.
Suggested next steps
  1. Replenish ACUs and run a full schematic/ERC review.
  2. Resolve any power, GPIO, or interface warnings.
  3. Generate firmware documentation from the finalized pin map.
  4. Review the schematic before proceeding to PCB layout.
Review and fix ERC
Check power budget
Create pin-map documentation
Prepare PCB layout

U12
U6
U10
J3
J6
U11
U1
Manufacturer Part Number
ESP32-S3-WROOM-1-N16R8
U8
U7
U9
D1
U13
J1
U2
R1
Resistance
10kΩ
R55
Resistance
732kΩ
R4
Resistance
10kΩ
R26
Resistance
1kΩ
R29
Resistance
1kΩ
R49
Resistance
59kΩ
R10
Resistance
10kΩ
R43
Resistance
33Ω
R18
Resistance
10kΩ
R17
Resistance
10kΩ
R6
Resistance
10kΩ
R9
Resistance
10kΩ
R48
Resistance
130Ω
R11
Resistance
10kΩ
R12
Resistance
10kΩ
R44
Resistance
33Ω
R3
Resistance
10kΩ
R34
Resistance
1kΩ
R46
Resistance
33Ω
R24
Resistance
1kΩ
R20
Resistance
4.7kΩ
R58
Resistance
100kΩ
R15
Resistance
10kΩ
R36
Resistance
1kΩ
R56
Resistance
22Ω
R2
Resistance
10kΩ
R13
Resistance
10kΩ
R45
Resistance
33Ω
R27
Resistance
1kΩ
R57
Resistance
100Ω
R7
Resistance
10kΩ
R22
Resistance
1kΩ
R14
Resistance
10kΩ
R8
Resistance
10kΩ
R47
Resistance
20mΩ
R32
Resistance
1kΩ
R5
Resistance
10kΩ
R41
Resistance
33Ω
R53
Resistance
100kΩ
R30
Resistance
1kΩ
R21
Resistance
1kΩ
R42
Resistance
33Ω
R37
Resistance
33Ω
R38
Resistance
33Ω
R31
Resistance
1kΩ
R51
Resistance
100kΩ
R50
Resistance
100kΩ
R25
Resistance
1kΩ
R33
Resistance
1kΩ
R19
Resistance
4.7kΩ
R23
Resistance
1kΩ
R52
Resistance
100kΩ
R16
Resistance
10kΩ
R35
Resistance
1kΩ
R60
Resistance
100kΩ
R40
Resistance
33Ω
R28
Resistance
1kΩ
R39
Resistance
33Ω
R59
Resistance
200kΩ
R54
Resistance
312kΩ
C13
Capacitance
10uF
C20
Capacitance
10uF
C28
Capacitance
100nF
C5
Capacitance
10uF
C17
Capacitance
10uF
C2
Capacitance
10uF
C18
Capacitance
10uF
C40
Capacitance
100pF
C33
Capacitance
47nF
C11
Capacitance
10uF
C10
Capacitance
10uF
C1
Capacitance
10uF
C26
Capacitance
100nF
C23
Capacitance
100nF
C36
Capacitance
1nF
C29
Capacitance
100nF
C38
Capacitance
1nF
C15
Capacitance
10uF
C24
Capacitance
100nF
C9
Capacitance
10uF
C21
Capacitance
100nF
C3
Capacitance
10uF
C34
Capacitance
1uF
C22
Capacitance
100nF
C32
Capacitance
100nF
C19
Capacitance
10uF
C35
Capacitance
1nF
C4
Capacitance
10uF
C37
Capacitance
1nF
C8
Capacitance
10uF
C12
Capacitance
10uF
C6
Capacitance
10uF
C30
Capacitance
100nF
C25
Capacitance
100nF
C27
Capacitance
100nF
C31
Capacitance
100nF
C7
Capacitance
10uF
C14
Capacitance
10uF
C16
Capacitance
10uF
C39
Capacitance
1nF
TP9
TP6
J8
TP11
J5
J7
TP5
TP8
TP2
TP1
TP10
J4
TP7
TP3
TP4
TP12
U5
J11
J10
J9
U4
D3
D2
D4
U22
U18
U16
SW2
U15
U17
U19
U20
SW1
L4
Inductance
1.5uH
J2
D5
U21
L5
Inductance
1uH
L3
Inductance
2.2uH
U3
Q1
U14
Project Specification
Product Vision
A modular, battery-powered field toolkit for authorized hardware and wireless security research. The product will begin as an accessible proof-of-concept platform and later be reduced into a sealed, weather-resistant handheld.
Intended Use and Safety Boundary
  • Authorized testing, device development, diagnostics, protocol analysis, and laboratory/field research only.
  • Firmware should include clear transmit controls, regional radio configuration, and safeguards against accidental continuous transmission.
  • The design must not assume permission to access, interfere with, or impersonate third-party systems.
Development Strategy
Phase 1 — Modular Proof of Concept
Build a larger, serviceable platform that validates the architecture and interfaces. Use modules and accessible headers where practical so failures and substitutions are easy to diagnose.
Phase 2 — Integrated Handheld
Consolidate validated functions onto a smaller PCB, optimize standby power and RF coexistence, and develop a sealed enclosure with protected external interfaces.
Phase 1 Functional Requirements
Processing and User Interface
  • ESP32-S3-class primary controller with Wi-Fi and BLE for development, connectivity, and user-interface tasks.
  • Color display readable outdoors.
  • Physical keyboard or directional controls plus dedicated power and back controls.
  • microSD storage for firmware, logs, captures, and configuration.
  • USB-C for charging, firmware updates, serial console, and USB device/host experiments where supported.
  • Audible and haptic feedback as optional populated features.
Radio and Optical Interfaces
  • 13.56 MHz NFC/RFID reader/writer module for authorized tag and protocol development.
  • Sub-GHz transceiver module covering permitted regional ISM bands, with replaceable or region-specific RF sections preferred for the prototype.
  • Infrared transmit and receive.
  • Wi-Fi and BLE through the primary controller.
  • RF sections must have independent power gating and clearly defined antenna keepouts.
Wired Hardware Debugging
  • Protected UART, I2C, SPI, and general-purpose GPIO interface.
  • Selectable target logic voltage, initially 1.8 V, 3.3 V, and 5 V where technically appropriate.
  • Input protection, current limiting, and clear pin labeling.
  • Target power output must be switchable and current-limited; it must default off.
  • Optional SWD/JTAG support through a dedicated debug header or adapter module.
Expansion
  • Internal expansion connector exposing regulated power and digital buses.
  • External module connector designed so radio or debug boards can be replaced without redesigning the core platform.
  • Test points for all power rails and major buses.
Power Requirements
  • Rechargeable single-cell Li-ion/LiPo battery architecture for the prototype.
  • USB-C charging with battery protection, fuel gauging, thermal monitoring, and load sharing/power-path management.
  • Independent load switches for display, radios, SD card, sensors, and expansion modules.
  • Deep-sleep operation with wake from buttons, timer, USB, and selected external signals.
  • Phase 1 target: one working day of mixed active use and multi-week standby when radios and display are off. Final targets will be refined using measured prototype consumption.
Environmental and Mechanical Requirements
Phase 1
  • Serviceable enclosure with splash protection as a goal, not full sealing.
  • Conformal-coating compatibility and corrosion-resistant external connectors.
  • Operating-temperature goal of at least -10 °C to +50 °C, subject to battery limitations.
Phase 2
  • Sealed handheld enclosure targeting IP65 or better.
  • Gasketed seams, protected buttons, sealed or capped connectors, pressure equalization as needed, and no exposed microSD slot unless gasketed.
  • Outdoor-readable display window and glove-usable controls.
  • Battery must remain replaceable by service personnel or be safely retained and thermally managed.
Architecture Constraints
  • Prefer certified radio modules during Phase 1 to reduce RF and compliance risk.
  • Keep NFC, sub-GHz, Wi-Fi/BLE antennas physically separated and independently disabled.
  • Separate noisy power conversion and display signals from RF and NFC antenna regions.
  • Use ESD protection on every user-accessible electrical interface.
  • Avoid relying on one RF front end to cover incompatible frequency ranges.
Suggested Phase 1 Blocks
  1. ESP32-S3 compute and user-interface board.
  2. Battery charging, gauging, power-path, and switched-rail subsystem.
  3. Display, keyboard/buttons, haptic motor, and buzzer.
  4. microSD and USB-C subsystem.
  5. NFC module and antenna.
  6. Region-specific sub-GHz transceiver module and antenna connector.
  7. Infrared transmitter/receiver.
  8. Protected multi-voltage hardware-debug interface.
  9. Expansion and test connectors.
Validation Criteria for Phase 1
  • Boots reliably from battery and USB power.
  • Charges safely while operating and reports battery state.
  • Demonstrates deep sleep and independently switches off major loads.
  • Reads/writes a test microSD card.
  • Performs authorized NFC tag read/write tests.
  • Performs short-range packet transmit/receive tests in a permitted ISM band.
  • Sends and receives infrared test patterns.
  • Communicates over UART, I2C, and SPI at each supported logic level without damaging the target or toolkit.
  • Logs test results locally and can export them over USB or wireless connectivity.
  • Records measured active and standby consumption to guide Phase 2 battery sizing.
Deferred Until After Phase 1
  • Final IP-rated enclosure and production sealing process.
  • Fully integrated custom RF matching networks and compact shared mechanical antenna system.
  • Production certification, emissions testing, and region-specific product variants.
  • Aggressive miniaturization, final industrial design, and production cost optimization.
  • Final firmware feature set and application/plugin ecosystem.
Immediate Next Step
Create the Phase 1 system block diagram and power budget, then select the core modules and define connector boundaries before schematic capture.
  • Product Vision

  • Intended Use and Safety Boundary

  • Development Strategy

  • Phase 1 — Modular Proof of Concept

  • Phase 2 — Integrated Handheld

  • Phase 1 Functional Requirements

  • Processing and User Interface

  • Radio and Optical Interfaces

  • Wired Hardware Debugging

  • Expansion

  • Power Requirements

  • Environmental and Mechanical Requirements

  • Phase 1

  • Phase 2

  • Architecture Constraints

  • Suggested Phase 1 Blocks

  • Validation Criteria for Phase 1

  • Deferred Until After Phase 1

  • Immediate Next Step