GND und Neutralleiter Erklärung
Thought for 29 sec
Ja - für dein Ziel sind 2 USB-C-Ports sinnvoll, also je einer pro ESP32.
Ich habe den überflüssigen dritten Port entfernt:
Damit bleibt jetzt die saubere Aufteilung:
Das ist auch die richtige Richtung für deinen Anwendungsfall:
- 1 Port pro MCU
- kein zusätzlicher dritter Debug-/Flash-Port ohne klaren Zweck
- weniger Platzbedarf, weniger Verwirrung, weniger unnötige USB-Beschaltung
USB-Beschaltung prüfen
ESD-Schutz ergänzen
CC-Widerstände kontrollieren
Auto-Reset prüfen
Thought for 1 min 38 sec
- Removed J6
- Removed U5
- Removed R15
- Removed R16
- Removed C9
⚠️ Removed components had their net connections destroyed. Use the connections tool with a
view action to verify connectivity and re-wire any lost connections.Refine this doc
Ask about this doc
System architecture
- Form factor: DIN rail enclosure T2, 36 mm width.
- Board target size: 36 mm x 95 mm rectangular layout with 2 mm corner radius.
- Mains input: 230 VAC via top terminal block.
- Internal low-voltage rail: isolated 5 V from AC/DC converter module.
- Controller: ESP32-S3 module for Wi-Fi plus application control.
- Additional 802.15.4 radio: ESP32-H2 companion module for Zigbee, Thread, and Matter over Thread support.
- Ethernet: W5500 SPI Ethernet controller plus integrated-magnetics RJ45 connector.
- USB-C: one bottom edge connector for ESP32-S3 service and one dedicated USB-C connector for ESP32-H2 flashing.
- LED interface: central terminal block on the low-voltage side.
Key engineering decisions
- Use an isolated AC/DC module for 230 VAC to 5 V conversion to maintain mains safety boundaries and simplify DIN-rail implementation.
- Use an ESP32-S3 module instead of bare silicon to improve RF implementation and certification readiness.
- Add a dedicated IEEE 802.15.4 companion module because ESP32-S3 alone does not provide native 802.15.4.
- Use a 4-layer layout because the design includes mains isolation, RF, Ethernet, USB, and mixed-voltage digital routing.
- Place AC input at the top, LED terminal in the middle, and USB-C plus RJ45 on the bottom side to align with requested field wiring orientation.
- Keep the original USB-C port on ESP32-S3 and add a second dedicated USB-C programming path for ESP32-H2 to avoid shared-programming ambiguity.
- Replace the previous RMII PHY concept with a W5500 SPI Ethernet controller because ESP32-S3 does not provide a native RMII MAC path suitable for the removed LAN8720A architecture in this project.
- Use a dedicated 25 MHz 3.3 V oscillator for W5500 clocking instead of a crystal to simplify bring-up and avoid crystal load-cap tuning risk.
ESP32-H2 flashing assessment
- The existing USB-C connector J3 is wired directly to U1 native USB on IO19/IO20.
- U2 is connected to U1 only through UART0 using R5 and R6.
- The original design did not expose a dedicated USB data path to U2 and did not provide an explicit H2 download-mode hardware path separate from the main controller.
- ESP32-H2 datasheet facts used for the decision:
- native USB Serial/JTAG is available on IO26 = USB_D- and IO27 = USB_D+
- UART0 is available on RXD0/TXD0
- Joint Download Boot requires GPIO8 = HIGH and GPIO9 = LOW during reset sampling
- Conclusion: U2 was not reliably or efficiently flashable through the original J3 service connector without additional control logic and firmware cooperation from U1.
Dedicated H2 programming interface
- Added J5 as a dedicated USB-C receptacle for U2 firmware flashing.
- Added D2 as USB ESD protection for the new H2 USB port.
- Added R10 and R11 as 5.1k CC pull-down resistors for the new USB-C port.
- Added C11 as local VBUS bypass on the new programming connector.
- Wired the new port directly to U2 native USB:
- Added R12 and R13 to bias H2 boot strap nets:
- H2_BOOT_GPIO8 pulled HIGH
- H2_BOOT_GPIO9 pulled LOW
- This dedicated interface separates H2 flashing from S3 service access and avoids contention on the inter-processor UART link.
Ethernet implementation
- U3 is the W5500 hardwired TCP/IP SPI Ethernet controller.
- J2 remains the integrated-magnetics RJ45 connector.
- C6 = 4.7uF on W5500 TOCAP.
- C7 = 10nF on W5500 1V2O.
- R7 = 10k pull-up on W5500 chip select.
- R8, R9, and R14 = 10k pull-ups on PMODE0, PMODE1, PMODE2 for strap mode 111.
- X1 provides the 25 MHz 3.3 V oscillator clock into W5500 XI/CLKIN.
- W5500 power wiring:
- VDD and all AVDD pins tied to 3V3.
- GND and all AGND pins tied to GND.
- RSVD pins tied to GND per datasheet requirement.
- VBG intentionally left floating per datasheet requirement.
- XO intentionally left unconnected because the oscillator drives XI/CLKIN directly.
- W5500 control and SPI wiring to U1:
- ETH_CS -> U1 IO12 -> U3 ~SCS
- ETH_SCLK -> U1 IO13 -> U3 SCLK
- ETH_MOSI -> U1 IO11 -> U3 MOSI
- ETH_MISO -> U1 IO10 -> U3 MISO
- ETH_INT -> U1 IO14 -> U3 ~INT
- ETH_RST_N -> U1 IO21 -> U3 ~RST
- W5500 MDI pair wiring to J2:
- TXP -> J2 pin 1
- TXN -> J2 pin 2
- RXP -> J2 pin 3
- RXN -> J2 pin 6
- The legacy RMII-only GPIO assignments on U1 were disconnected to remove stale Ethernet architecture remnants.
- RJ45 LED pins are still open for a later revision. If front-panel Ethernet indication is desired, route W5500 LINKLED and ACTLED through current-limiting resistors to the MagJack LED pins or to discrete indicators.
Schematic partitioning
- AC mains block: J1, F1, RV1, PS1.
- 5 V and 3.3 V power block: C1, C2, U4, C3, C4, C8, FB1.
- Main controller block: U1 with decoupling and boot/enable resistors.
- 802.15.4 companion block: U2 with UART link to U1 and a dedicated USB flashing port.
- Ethernet block: U3, X1, C6, C7, R7, R8, R9, R14, J2.
- USB service block for S3: J3, R1, R2, D1.
- USB flashing block for H2: J5, D2, R10, R11, R12, R13, C11.
- LED field I/O block: J4.
Layout guidance
- Keep the entire mains block at the top edge with clear isolation from the low-voltage domain.
- Keep the LED connector near the board center for harness accessibility.
- Keep the USB-C connectors on the bottom edge.
- Keep the RJ45 connector on a board edge in the lower half of the layout.
- Keep RF modules away from the AC/DC module and away from the RJ45 shield region as much as possible.
- Place X1, C6, C7, and R7 adjacent to U3.
- Keep USB ESD protection directly adjacent to J3 and J5.
- Place J5 so the DIN-rail front access remains within the 36 mm enclosure width; use the board length direction for connector spacing rather than increasing width.
- During Ethernet placement, keep the U3 to J2 differential pairs short and direct, and keep the oscillator trace from X1 to U3 XI/CLKIN short.
Open items for follow-up
- Add explicit mains creepage documentation and safety review.
- Decide whether the RJ45 LED pins should be wired to W5500 LED outputs or left unused in the first PCB revision.
- If completely automatic H2 boot entry is desired from a host PC without manual intervention, add a reset/download gating circuit for EN and strap control in a later revision.
- Finish PCB placement and routing around the Ethernet and mains isolation regions, then resolve remaining airwires and final DRC issues.
System architecture
Key engineering decisions
ESP32-H2 flashing assessment
Dedicated H2 programming interface
Ethernet implementation
Schematic partitioning
Layout guidance
Open items for follow-up
