Smart 12V Power Controller Design
2:24
Planning component placement.
Proposing board adjustments.
Assessing keepouts for layout.
Clarifying board specifications.
Determining board dimensions and placements.
Accessing knowledge base.
Checking if I can make the changes for you.
Finalizing component placements and board size.
I can resize the PCB to 190 mm × 110 mm now. After that, use the placement plan below to manually place parts. All coordinates are in mm, origin at board bottom‑left, positive X to the right, positive Y up. Keep 5 mm edge keepout everywhere, and 10 mm keepout around each M8 stud.
Top edge: eight M8 studs (custom STUD_M8_RINGPAD, 8.5 mm PTH, 20 mm OD, 10 mm keepout)
- Y = 105
- X positions (left to right, 22 mm pitch): 20, 42, 64, 86, 108, 130, 152, 174
- Net mapping:
- X=20 BAT+
- X=42 BAT−
- X=64 LOAD+
- X=86 LOAD−
- X=108 PV_OUT+
- X=130 PV_OUT−
- X=152 EXT_OUT+
- X=174 EXT_OUT−
Mounting holes (M3, 90 × 70 rectangle)
- Hole1: (50, 20)
- Hole2: (140, 20)
- Hole3: (50, 90)
- Hole4: (140, 90)
Star ground and current sensor
- Place star‑ground tie at (42, 92) near U3
- U3 ACS71240: (42, 92), rotate 0°. Route the main VBAT path past U3 per your sense direction.
Power entry and reverse‑polarity + TVS
- U1 LM5050‑1: (28, 92), R=0°
- D1 SMBJ12A: (24, 86), R=0°
- D2 SMBJ12A: (32, 86), R=0°
- Keep U1, D1, D2 close to BAT studs (X=20/42), with very short/wide copper to studs and to VBAT bus.
Coil rail, global enable, and low‑side drivers
- +12V_COIL rail: route from F_COIL output to coil connectors; keep isolated from logic until entry to drivers.
- F1 coil fuse: (165, 78), R=90°
- J4 COIL_ENABLE 1×3: (115, 60), R=0° (Pin1=COIL_ENABLE, Pin2=GND, Pin3=+5V_LOGIC)
Right edge: coil connectors (2‑pin 5.08 mm)
- J_KLOAD_COIL: (185, 80), R=180° (Pin1=+12V_COIL toward inside)
- J_KPV_COIL: (185, 60), R=180°
- J_KEXT_COIL: (185, 40), R=180°
Low‑side MOSFET drivers (close to their connectors; gates face inward)
Logic, comparators, and headers (left/center)
- U2 LM393: (70, 62), R=0°. Keep its hysteresis/sense resistors within 5 mm of pins.
- J_OUT 1×8: (12, 70), R=90° (Pin1 at top)
- J_IN 1×8: (12, 50), R=90°
- J_ADC 1×8: (12, 30), R=90°
- J_PWR 1×4: (28, 30), R=0°
Bottom edge: PV/EXT sense and buzzer
- J_PV_SENSE: (20, 6), R=0°
- J_EXT_SENSE: (46, 6), R=0°
- BZ1 TMB12A05: (80, 8), R=0°
- Q4 (buzzer MOSFET): (74, 10), R4 gate series: (72, 10)
Inductors/placeholders for buck area (logic power)
- L1: (100, 62), L2: (110, 62). Reserve local area for 12V→5V buck controller and bulk caps; keep away from comparators and ADC headers.
Notes for manual placement
- Keep all decoupling caps (C1–C13) within 2–3 mm of their IC power pins; shortest loop to ground via.
- Run the high‑current plane along the top under the studs; no signal vias/traces inside each stud’s 10 mm keepout.
- Maintain clear separation between high‑current copper (top edge) and logic (lower half). Leave a routing channel between headers and drivers.
- After placement, use airwires to assess routing feasibility and adjust spacing before autorouting (knowledge base: leave space for routing and vias; use airwires to visualize paths).
- Keep OV/UV thresholds exactly 14.8/14.4 V and 11.6/12.2 V; don’t alter those networks during placement.
Would you like me to apply the PCB resize to 190 × 110 mm now? Once resized, follow the coordinates above to place the components manually, and I can iterate on any conflicts you notice during routing.
86 days
Updated 1 layout rule
0:11
Set Layout's size to "190mm 110mm
"
86 days
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