Project Specification
Project Overview
First-pass professional SMD schematic for rebuilding only the low-voltage television power and tap-control functions. Status: Draft / schematic checkpoint.
Intended Use
Prototype/validation board powered by a dedicated USB-C 5 V supply. It replaces selected low-voltage rails and exposes a piezo tap signal to an externally plugged ESP32-C3 Supermini.
What the Device Should Do
- Accept 5 V through a power-only USB-C sink receptacle.
- Protect and filter the input, then generate 3.3 V and 8 V television rails.
- Generate provisional P8_REF near 1.038 V from 8 V.
- Condition a piezo pulse into an ADC-safe TAP_ADC signal.
Main Features
- Independent 5.1 kΩ Rd on CC1 and CC2; no USB data or PD negotiation.
- TPS628302ADRLR 3.3 V/2 A buck.
- LT1935ES5 boost adapted to 8 V, with allowed load limited by verified switch/thermal capability.
- External ESP32 header carrying TAP_ADC, 3V3, and GND; module powered separately by its own USB.
- Bring-up test access on critical rails where practical.
System Architecture
See Block Diagram project file.
Hardware Subsystems
- USB-C input, overcurrent protection, 5 V TVS, input bulk and HF capacitance.
- 3.3 V synchronous buck with EN tied to VIN, MODE low, PG pull-up, LC/output network and feedback divider per exact datasheet.
- 8 V boost with inductor, Schottky rectifier, feedback divider and valid capacitors per LT1935 datasheet.
- P8 divider and optional justified filter capacitor.
- Piezo rectifier/envelope and low-leakage ADC clamp.
- Input/output connectors and critical test points.
Interfaces and Connections
Named nets: USB_5V_RAW, 5V_PROTECTED, 3V3_TV, 8V_TV, P8_REF, PIEZO_RAW, TAP_ADC, GND.
Power and Runtime Expectations
Continuous external supply. A dedicated regulated 5 V/3 A USB-C source and low-loss cable are required. The source must advertise/supply the required current; CC current-advertisement detection is not implemented, so connection to ordinary default-current USB ports is not permitted.
Power Tree and Power Budget
See Power Budget project file.
Manufacturing and Assembly Expectations
Professional SMD PCB. Prefer leaded/hand-solderable IC packages and 0603/0805 passives where electrically practical. PCB layout is explicitly out of scope for this checkpoint.
Firmware-Relevant Hardware Requirements
Firmware samples TAP_ADC on the external ESP32-C3. Apply a 30–50 ms lockout after a valid tap. Lockout is firmware-only.
Physical Design Expectations
Connector accessibility and compact power loops will be addressed during the later PCB phase. No board dimensions are yet specified.
Important Design Decisions
- No PD controller; 5 V only.
- ESP32-C3 Supermini is not powered from this board.
- No mains PSU, CCFL inverter, 13 V audio rail, or PROTECT3 bypass.
- P8 function is unconfirmed and must be validated against the target TV harness before use.
Assumptions
- USB input may droop to 4.5 V at the protected converter input for worst-case budgeting.
- Conservative first-pass efficiency: 85% for both rails.
- Peak loads: 3.3 V at 2.0 A and requested 8 V at 0.5 A, subject to LT1935 verification.
Change Notes
- Initial specification created from the Desk Screen Rebuild requirements.