Temperature and Humidity Sensor Design
1:05
Accessing knowledge base.
- Spodní keep‑out: kruh Ø38 mm, blokuje měď, průchodky i součástky; pouze bottom vrstvy.
- M3 NPTH: Hole5/Hole6 symetricky, 1.5 mm copper keep‑out.
- Výkon: flip Q1/Q2 na spodní, osadit nad keep‑out; přidat hustý via‑plot u okraje (na GND).
- Ostatní: J1–J4 a malé signály zůstanou nahoře; ověřím krátké di/dt smyčky; spustím DRC.
- Modify the existing Ø73 mm circular PCB for the Desirable Apricot Holodeck by adding a bottom-side heatsink keep-out area, relocating the power MOSFETs (Q1/Q2) to the bottom over the designated area, and maintaining all connectors and small-signal parts (J1–J4 and others) on the top. Validate the layout via DRC to ensure design rule compliance.
- Define heatsink keep-out zone on the bottom layer:
- Create a centered circular keep-out region (Ø38 mm) on the bottom layer that prevents copper, vias, and component placement within the heatsink area.
- Lock the keep-out to affect only the bottom layer.
- Update NPTH hole placement for symmetric mounting:
- Position NPTH holes Hole5 and Hole6 symmetrically around the board center.
- Add a 1.5 mm copper keep-out or clearance ring around each of these holes to avoid interference with the bottom heatsink area.
- Relocate power MOSFETs:
- Move Q1 and Q2 (IPT012N08N5) to the bottom side, positioning them over the defined heatsink keep-out zone.
- Add a dense thermal via fence around the perimeter of the keep-out area, connecting to the bottom layer GND (L2), to enhance thermal performance.
- Maintain connectors and small-signal components on the top side:
- Ensure that J1–J4 (282837-2 and 0022232031) and small-signal parts (e.g., U2 INA180A1, U5 LM393ADR, other passive components) remain on the top layer.
- Verify that power supply routing and high di/dt loops remain short, as per design requirements.
- Run DRC validation:
- Execute a Design Rule Check (DRC) to identify and resolve any clearance or placement violations due to the modifications.
- The bottom layer features a clearly defined Ø38 mm keep-out area for the heatsink that blocks copper, vias, and components.
- Power MOSFETs Q1/Q2 are relocated to the bottom layer and positioned over the heatsink keep-out, with an adjacent thermal via fence tied to GND.
- All connectors and small-signal components remain exclusively on the top layer.
- DRC results show no rule violations related to clearance, component placement, or keep-out conflicts.
Started implementing a plan
#Goal
- Modify the existing Ø73 mm circular PCB for the Desirable Apricot Holodeck by adding a bottom-side heatsink keep-out area, relocating the power MOSFETs (Q1/Q2) to the bottom over the designated area, and maintaining all connectors and small-signal parts (J1–J4 and others) on the top. Validate the layout via DRC to ensure design rule compliance.
#Implementation plan
1. Define heatsink keep-out zone on the bottom layer:
1. Create a centered circular keep-out region (Ø38 mm) on the bottom layer that prevents copper, vias, and component placement within the heatsink area.
2. Lock the keep-out to affect only the bottom layer.
2. Update NPTH hole placement for symmetric mounting:
1. Position NPTH holes Hole5 and Hole6 symmetrically around the board center.
2. Add a 1.5 mm copper keep-out or clearance ring around each of these holes to avoid interference with the bottom heatsink area.
3. Relocate power MOSFETs:
1. Move Q1 and Q2 (IPT012N08N5) to the bottom side, positioning them over the defined heatsink keep-out zone.
2. Add a dense thermal via fence around the perimeter of the keep-out area, connecting to the bottom layer GND (L2), to enhance thermal performance.
4. Maintain connectors and small-signal components on the top side:
1. Ensure that J1–J4 (282837-2 and 0022232031) and small-signal parts (e.g., U2 INA180A1, U5 LM393ADR, other passive components) remain on the top layer.
2. Verify that power supply routing and high di/dt loops remain short, as per design requirements.
5. Run DRC validation:
1. Execute a Design Rule Check (DRC) to identify and resolve any clearance or placement violations due to the modifications.
#Success criteria
- The bottom layer features a clearly defined Ø38 mm keep-out area for the heatsink that blocks copper, vias, and components.
- Power MOSFETs Q1/Q2 are relocated to the bottom layer and positioned over the heatsink keep-out, with an adjacent thermal via fence tied to GND.
- All connectors and small-signal components remain exclusively on the top layer.
- DRC results show no rule violations related to clearance, component placement, or keep-out conflicts.
Adding bottom keep-out zone...
0:44
Started: Add a circular keep-out region on the bottom layer, 38 mm diameter, centered on the board
Updated 1 layout rule
0:27
Stopped due to a problem. Please try again.
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