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Schematic

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Schematic of [Multi-layer] JLCPCB Constraints
DS1
T6
T2
SW1
D5
R6
Resistance
1kΩ
FS1
R3
Resistance
1kΩ
R4
Resistance
1kΩ
R2
Resistance
1kΩ
D4
R5
Resistance
1kΩ
R1
Resistance
1kΩ
FS3
FS2
U4
T13
T9
T4
Q1
T11
C1
Capacitance
Capacitance
T5
T1
T12
T3
LED2
C11
Capacitance
1uF
T10
C12
Capacitance
1uF
LED1
R8
End of Life
SW2
D12
D9
U8
U5
R7
End of Life
C10
Capacitance
100uF
Y1
D3
D2
U10
C9
Capacitance
100uF
D10
D1
R1
Resistance
500 Ω
T8
D11
D8
D13
T7
D6
D7
U9
S1
J3
J1
L1
Inductance
Inductance
C1
Capacitance
100pF
U1
LED3
BZ2
J2

[Multi-layer] JLCPCB Constraints