USB-C WiFi BLE Sensor Design
Worked for 3 mins 22 sec
I started the USB-C Wi‑Fi/BLE temperature/humidity sensor node design and completed the early schematic setup work before execution stopped.
Completed:
- Renamed the project to USB-C WiFi BLE Environmental Sensor and updated the description.
- Created initial project files:
- Selected and added the main schematic parts:
- U1: ESP32-C3-MINI-1-N4 Wi‑Fi 802.11 b/g/n + BLE 5 module
- U2: SHT40-AD1F-R2 digital temperature/humidity sensor
- U3: TPS259474LRPWR eFuse for OVP/UVLO/OCP/reverse-current protection
- U4: AP63203WU-7 3.3 V / 2 A buck regulator
- J1: USB-C receptacle
- D1: TPD2EUSB30A USB D+/D− ESD protection
- Consulted datasheets for the ESP32-C3 module, SHT40 sensor, TPS25947 eFuse, AP63203 buck regulator, and USB ESD protector.
Key design decisions already grounded in datasheets:
- ESP32-C3 requires 3.0–3.6 V, with a supply sized for at least 0.5 A.
- ESP32-C3 USB native pins are IO18 = USB_D− and IO19 = USB_D+.
- ESP32-C3 EN must not float; datasheet recommends an RC delay, typically 10 kΩ + 1 µF.
- SHT40 runs from 1.08–3.6 V, uses I2C address 0x44, and needs 100 nF decoupling.
- AP63203 fixed 3.3 V buck recommended external parts:
- 10 µF input capacitor
- 3.9 µH inductor
- 2 × 22 µF output capacitors
- 100 nF bootstrap capacitor
- TPS259474 eFuse:
- IN range 2.7–23 V
- Adjustable UVLO/OVLO
- ILM resistor required; do not leave ILM floating
- ITIMER may be left open for fastest overcurrent response or populated with a capacitor for blanking
- PG is open-drain and needs pull-up if used
Remaining work:
- Add all support passives: USB-C CC pull-downs, buck inductor/caps, eFuse threshold/current-limit parts, ESP32 EN/reset/boot parts, I2C pull-ups, decoupling, LED, and test points.
- Wire the full schematic.
- Run ERC/review and fix all violations.
- Create firmware starter and board bring-up plan files.
- After schematic is clean, ask for approval before moving to PCB layout.
Finish schematic
Size eFuse resistors
Complete USB-C
Run ERC/DRC
Document decisions
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Ask about this doc
Power Budget
Loads on 3.3 V Rail
Table
| Load | Sleep | Typical Active | Peak |
|---|---|---|---|
| ESP32 Wi-Fi/BLE module | tens of uA target in sleep | ~80–160 mA during connected operation | design for 500 mA radio burst margin |
| Digital T/RH sensor | sub-uA to uA sleep | <1 mA measurement average | a few mA during conversion |
| Status LED | 0 mA off | 1–5 mA on | 5 mA |
| Pull-ups/control leakage | negligible | <1 mA | <1 mA |
Sizing Result
Design 3.3 V rail for at least 600 mA peak to cover ESP32 radio bursts, sensor conversion, LED, and margin.
Input Current Reflection
With a switching regulator, approximate peak input current from 5 V is:
Iin = (3.3 V × 0.6 A) / (5 V × 0.85) ≈ 0.47 A.
Protection/Power-Path Sizing
- USB-C connector and VBUS path should support at least 3 A mechanically/electrically because user requested planning for 0.5–3 A sources.
- eFuse/current-limit path should be configurable near the product current requirement, with margin above the ~0.5 A peak estimate while protecting against faults.
- Regulator selected for ≥600 mA 3.3 V output, preferably ≥1 A for thermal/current margin.
Notes
The design must not assume it may draw 3 A from every USB-C source. CC pull-downs advertise sink mode; firmware or hardware current policy should stay below the board-set current limit unless a later revision adds explicit current advertisement detection or USB-PD.
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