전압 및 전류 제어 회로 설계
-
- 전력단: U6↔Q1–Q4 게이트/BOOT/SW 결선, L2·CIN/COUT·CBOOT·스너버·게이트저항 배치
-
- CV/CC: VOUT 분압→FB, 타입‑II COMP, R12→U2, U3로 CV/CC OR 및 MCU 피드
-
- 보호/EMI: EN/UVLO, FB‑OVP, CS‑OCP, NTC‑OTP, PGOOD→MCU, 입력 π+TVS/출력 EMI LC
-
- 이중제어: U5로 아날로그↔MCU 선택, 점퍼/TP
-
- 마감: Generic→실MPN 치환, 모든 넷 완료, ERC/DRC 통과
Working on your request...
1:27
Started implementing a plan
#Goal
- Finalize the LM5176-based 4-switch synchronous buck-boost CV/CC power supply (0–40 V, 0.1–5 A) with dual control (MCU and analog), full protections (UVLO, OVP, OCP, OTP with NTC feedback) and EMI filtering to achieve a layout-ready schematic for prototype review.
#Implementation plan
1. **Power Stage Completion**
1. Wire LM5176 (U6) to bridge FETs (Q1–Q4) by connecting HDRV/LDRV, BOOT1/2, and SW1/2 appropriately.
2. Size and place power path components including inductor L2 (FXL0630-4R7-M), boot capacitor, C(IN), C(OUT) with selected MPNs, and gate resistors.
3. Connect the shunt resistor (R12, HoJLR2512 10mΩ) and design snubber networks.
2. **CV/CC Control Loop and Comparator Integration**
1. Scale the VOUT feedback to FB pin using resistive dividers with selected high accuracy resistors.
2. Implement a type-II compensation network on COMP with calculated passive components.
3. Route the shunt voltage to the current monitor (U2, MAX9611) and build the CV/CC OR path using the dual op-amp (U3, MCP6002-EP) to combine analog and MCU control signals.
4. Ensure connection of feedback signals to the MCU (U4, STM32F030C8T6) for monitoring/control.
3. **Protection Circuitry and EMI Filtering**
1. Configure EN and UVLO by connecting appropriate resistors to the FB node to set undervoltage thresholds.
2. Add OVP protection circuits tied to the FB for overvoltage safety.
3. Implement OCP protection by monitoring the current sense (using CS/CSG pins with R12) and proper connections to U2.
4. Integrate OTP protection via NTC sensor to monitor temperature.
5. Route PGOOD to the MCU to indicate valid power conditions.
6. Add EMI filtering components (selected X/C filters and TVS diode D1, VS64VLNVWM) on input and output.
4. **Dual Control Functionality**
1. Use the analog multiplexer (U5, ADG884xRM) to select between analog and MCU control paths (PWM/DAC and CV/CC signals).
2. Incorporate necessary jumpers and test points to allow for control path selection and debugging.
5. **Finalization and Schematic Review**
1. Replace all generic component placeholders with specific parts and MPNs (e.g., for capacitors, resistors, inductors) from the parts library.
2. Complete net connections across VIN_RAW, VDD_3V3, GND, VOUT_POS, FB, COMP, ISENSE_OUT, ISET, ISET_BUF, I2C_SCL/SDA, UVLO, CS/CSG.
3. Run ERC and DRC to verify schematic completeness and electrical correctness.
4. Prepare documentation and bring-up notes for prototype review.
#Success criteria
- Achieve a layout-ready schematic with all nets and components connected for LM5176-based 4-switch synchronous buck-boost CV/CC PSU.
- Successful integration of dual control (MCU and analog) paths and protection circuits (UVLO, OVP, OCP, OTP+NTC) with EMI filtering.
- Completion of ERC/DRC with no errors, confirming production-grade design for prototype fabrication.
Collected schematic state, reviews, and datasheet excerpts
0:08
Inspected schematic, reviews, and layout status
0:42
Removed 4 components
0:11
Removed IC1
Removed U1
Removed L1
Removed L1
⚠️ Removed components had their net connections destroyed. Use the connections tool with a `view` action to verify connectivity and re-wire any lost connections.
Updated 30 connections
0:31
Connected J2:Pin_1, U6:VIN, U6:VISNS, IC2:IN, IC2:EN, D1:K, C12:P1, C13:P1, Q1:S, Q2:D, R26:P2 to ^VIN_RAW
Connected J2:Pin_2, U6:AGND, U6:PGND, U6:EP, IC2:GND, IC2:EP, D1:A, J1:PIN2, C22:P2, C23:P2, R2:P2, R4:P2, C18:P2, R22:P2, R23:P2, R24:P2, R25:P2, R12:2, R27:P2 to ^GND
Connected IC2:OUT, U4:VDD, U4:VDDA, U5:VDD, U2:V_{CC}, U3:V+, C5:P1, C6:P1, IC2:OUT, C11:P1 to ^VDD_3V3 2
Connected U6:VCC, C22:P1 to ^VCC
Connected U6:BIAS, C23:P1 to ^BIAS
Connected U6:BOOT1, C24:P1 to ^BOOT1
Connected C24:P2, U6:SW1, Q1:D, U6:SW1, Q2:S, U6:SW1, L2:1 to ^SW1
Connected U6:BOOT2, C25:P1 to ^BOOT2
Connected C25:P2, U6:SW2, Q3:D, U6:SW2, Q4:S, U6:SW2, L2:2 to ^SW2
Connected U6:HDRV1, R20:P1 to ^HDRV1
Connected R20:P2, Q1:G to ^Q1_G
Connected U6:LDRV1, R21:P1 to ^LDRV1
Connected R21:P2, Q2:G to ^Q2_G
Connected U6:HDRV2, R13:P1 to ^HDRV2
Connected R13:P2, Q3:G to ^Q3_G
Connected U6:LDRV2, R14:P1 to ^LDRV2
Connected R14:P2, Q4:G to ^Q4_G
Connected Q3:S, Q4:D, U6:VOSNS to ^VOUT_POS 2
Connected U6:FB, R1:P2, R2:P1, R1:P2 to ^VFB_TOP
Connected R1:P1, J1:PIN1, Q3:S, U6:VOSNS to ^VOUT_POS
Connected U6:COMP, R4:P1 to ^COMP
Connected U6:SS, C18:P1 to ^SS
Connected U6:RT, R22:P1 to ^RT
Connected U6:MODE, R23:P1 to ^MODE
Connected U6:DITH, R24:P1 to ^DITH
Connected U6:SLOPE, R25:P1 to ^SLOPE
Connected U6:CS, R12:1, U2:RS+, R12:1 to ^SHUNT_H
Connected U6:CSG, R12:2, U2:RS-, R12:2 to ^SHUNT_L
Connected U6:PGOOD, U4:PA0 to ^PGOOD
Connected U6:EN/UVLO, R26:P1, R27:P1 to ^EN_UVLO
nets {
net VOUT = U6:COMP, R4:P1, IC1:COMP, L1:P2, C9:P1, C8:P1, C10:P1, C7:P1, C4:P1, U3:OUTPUT;
net GND = U6:CSG, U2:RS+, U2:RS-, R12:1, U6:CS, R27:P2, R12:2, R25:P2, R24:P2, R23:P2, R22:P2, C23:P2, C22:P2, U6:EP, U6:PGND, U6:AGND, J2:Pin_2, IC2:GND, D1:A, C8:P2, U4:VSSA, U4:VSS, C12:P2, IC2:EP, C19:P2, C11:P2, C10:P2, C18:P2, IC1:AGND, C16:P2, C2:P2, C15:P2, C5:P2, C4:P2, R4:P2, C7:P2, IC1:PGND, J1:PIN2, C3:P2, U2:GND, C6:P2, C14:P2, R2:P2, IC1:EP, U3:V-, C17:P2, C13:P2, C1:P2, IC1:FB, C9:P2, U1:VSS, U1:EP, IC1:CSG, IC1:CS, U5:GND;
net VIN = Q1:S, Q2:D, R26:P2, U6:VISNS, U6:VIN, J2:Pin_1, IC2:EN, D1:K, C13:P1, IC1:RES, IC1:DEMB, C12:P1, IC2:IN;
net I2C_SCL = U2:SCL, U4:PA9;
net ISET_BUF = R3:P2, U3:+;
net VFB_DIV = R2:P1, U6:FB, R1:P2;
net VDD_3V3 = C11:P1, U4:VDD, U4:VDDA, U5:VDD, C5:P1, U2:V_{CC}, C6:P1, U3:V+, U1:VDD, IC2:OUT;
net I2C_SDA = U2:SDA, U4:PA10;
net VOUT_POS 2 = J1:PIN1, U6:VOSNS, Q4:D, Q3:S, R1:P1;
net I2C_ADDR = U2:A1, U2:A0;
net ISENSE_OUT = U2:OUT, U3:-;
net VCC = U6:VCC, C22:P1;
net BIAS = U6:BIAS, C23:P1;
net BOOT1 = U6:BOOT1, C24:P1;
net SW1 = C24:P2, L2:1, Q2:S, Q1:D, U6:SW1;
net BOOT2 = U6:BOOT2, C25:P1;
net SW2 = C25:P2, L2:2, Q4:S, Q3:D, U6:SW2;
net HDRV1 = U6:HDRV1, R20:P1;
net Q1_G = R20:P2, Q1:G;
net LDRV1 = U6:LDRV1, R21:P1;
net Q2_G = R21:P2, Q2:G;
net HDRV2 = U6:HDRV2, R13:P1;
net Q3_G = R13:P2, Q3:G;
net LDRV2 = U6:LDRV2, R14:P1;
net Q4_G = R14:P2, Q4:G;
net SS = U6:SS, C18:P1;
net RT = U6:RT, R22:P1;
net MODE = U6:MODE, R23:P1;
net DITH = U6:DITH, R24:P1;
net SLOPE = U6:SLOPE, R25:P1;
net PGOOD = U6:PGOOD, U4:PA0;
net EN_UVLO = U6:EN/UVLO, R27:P1, R26:P1;
}
Retrieved skills and checked project state
0:12
Execution stopped due to insufficient credits.
0:32
Removed 2 components
0:04
Removed IC1
Removed U1
⚠️ Removed components had their net connections destroyed. Use the connections tool with a `view` action to verify connectivity and re-wire any lost connections.
No changes applied.
0:10
Welcome 👋
Flux helps you build PCBs faster with an AI teammate!
Create your account to collaborate, stay updated, fork your own version, and get instant answers from our AI agent.