Raspberry Pi Pico Console
Thought for 4 sec
The next major phase is complete PCB routing. Placement and the critical debug USB/LED routes are ready, but most board connections remain unrouted.
Recommended order:
-
Route power and ground
- 5 V input, eFuse, hub power switch, Pico supply
- Ground and power-plane strategy across the six-layer stackup
- Add stitching vias and confirm current capacity
-
Route critical signals
- USB hub upstream and three downstream differential pairs
- PIO DVI/HDMI differential signals
- 24 MHz crystal and clock-sensitive connections
-
Route remaining low-speed signals
- Hub configuration, overcurrent, reset, UART/SWD and indicators
-
Run full-board validation
- Zero unintended airwires
- DRC, return-path, differential-pair and power-integrity checks
- Verify connector labels and silkscreen
-
Prepare manufacturing and software
- Gerbers, drill files, BOM and pick-and-place
- Finalize Pico firmware for USB MSC, FAT32 read/write, HID controllers, activity LEDs and video output
- Follow the board bring-up plan on the first assembled PCB
Completing routing and manufacturing preparation requires Agent mode.
Route power and signals
Check stackup readiness
Export manufacturing files
Review firmware mapping
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Project Specification
Architecture
Raspberry Pi Pico 2 console with one USB-C power/debug receptacle, CP2102N USB-to-UART debug, a separate PIO USB host link to a USB2504 hub, three protected USB-A ports, PIO DVI video on HDMI, SWD, and RUN reset.
USB-C D+/D− terminate only at CP2102N U5. U5 TXD drives Pico GPIO1 (UART0 RX) and U5 RXD is driven by Pico GPIO0 (UART0 TX). The omitted Pico native USB test pads are intentionally not used. Native USB programming through J1 is not required. Guaranteed programming/recovery is SWD plus RUN; BOOTSEL uses the Pico 2 module's onboard pushbutton. The module's onboard USB connector may be used during development only when physically accessible.
Final GPIO Allocation
Table
| Pico pin | Function |
|---|---|
| GPIO0 | UART0 TX to CP2102N RXD |
| GPIO1 | UART0 RX from CP2102N TXD |
| GPIO2 | PIO USB host D+ to USB2504 upstream |
| GPIO3 | PIO USB host D− to USB2504 upstream |
| GPIO4 | USB2504 RESET_N |
| GPIO5 | Controller 2 activity LED (active-high) |
| GPIO8/9 | PIO DVI TMDS data2 +/− |
| GPIO10/11 | PIO DVI TMDS data1 +/− |
| GPIO12/13 | PIO DVI TMDS data0 +/− |
| GPIO14/15 | PIO DVI TMDS clock +/− |
| GPIO16 | GAME cartridge activity LED (active-high) |
| GPIO17 | CONTROLLER 1 activity LED (active-high) |
| SWDIO/SWCLK | Guaranteed programming/debug |
| RUN | External reset switch and SWD header reset |
GPIO6-7 and GPIO18-28 are unused and explicitly no-connect. HDMI CEC, Utility, DDC SCL/SDA, and HPD are intentionally unused: firmware emits a fixed 640×480 DVI mode without EDID or HPD gating.
Power Tree
USB-C VBUS → TPS25200 eFuse/current limiter → PROTECTED_5V → Pico VSYS and TPS2054 downstream switches. CP2102N is bus-powered from raw USB VBUS and supplies its local 3.3 V regulator output/VIO. USB2504 uses 3V3 and its enabled internal 1.8 V regulator with required bypassing.
USB Hub
USB2504 uses a 24 MHz crystal, 12 kΩ RBIAS, internal-default strap mode, self-powered indication, and individual downstream data links. The role mapping follows hub-port numbering and existing net names: port 1 / J2 = GAME cartridge (standard USB MSC), port 2 / J3 = CONTROLLER 1 (USB HID), and port 3 / J4 = CONTROLLER 2 (USB HID). Each role has an independent active-high Pico-driven LED through 1kΩ: LED1 green on GPIO16 for GAME, LED3 blue on GPIO17 for CONTROLLER 1, and LED2 on GPIO5 for CONTROLLER 2. USB2504 PRTPWR1-3 drive TPS2054 EN1-3 and TPS2054 OC1-3 return to OCS1-3 with 10k pull-ups. Channel/port 4 is not exposed; TPS2054 EN4 is grounded and unused OC4/PRTPWR4/OCS4 are no-connect.
Interface Policy
USB and HDMI pair nets must carry explicit pair names and controlled-impedance metadata. USB pairs target 90 Ω differential. HDMI/DVI pairs target 100 Ω differential when completed.
Recovery and Programming
SWD is the guaranteed programming path. The external RUN switch remains. BOOTSEL recovery uses the module onboard button; no attempt is made to wire omitted native-USB/BOOTSEL test pads.
Scope Gate
Schematic only. No PCB placement or routing work is authorized in this phase.
Architecture
Final GPIO Allocation
Power Tree
USB Hub
Interface Policy
Recovery and Programming
Scope Gate
