Z80 Computer Project Overview

flux

1:55

Analyzing the schematic.

Avoiding specific references.

Detailing connections and requirements.

Considering adding the Z8420 part.

Preparing to list components.

Preparing the components table.

Here’s what’s placed in your schematic and the current net status.
Placed components

Table

DesignatorPartTerminal TypePin No.Category
VCCTerminalpowerIn26Power
GNDTerminalpowerIn11Ground
CLKTerminalINPUT25Clock
~{CE}TerminalINPUT4Z80 control
~{IORQ}TerminalINPUT36Z80 control
~{RD}TerminalINPUT35Z80 control
~{M1}TerminalINPUT37Z80 control
C/~{D}TerminalINPUT5PIO control
B/~{A}TerminalINPUT6PIO control
~{ASTB}TerminalINPUT16Handshake (Port A)
~{BSTB}TerminalINPUT17Handshake (Port B)
ARDYTerminaloutput18Handshake (Port A)
BRDYTerminaloutput21Handshake (Port B)
~{INT}TerminalopenCollector23Interrupt out
IEITerminalINPUT24Int. daisy-chain in
IEOTerminaloutput22Int. daisy-chain out
D0Terminalbidi19Z80 data bus
D1Terminalbidi20Z80 data bus
D2Terminalbidi1Z80 data bus
D3Terminalbidi40Z80 data bus
D4Terminalbidi39Z80 data bus
D5Terminalbidi38Z80 data bus
D6Terminalbidi3Z80 data bus
D7Terminalbidi2Z80 data bus
PA0Terminalbidi15Port A
PA1Terminalbidi14Port A
PA2Terminalbidi13Port A
PA3Terminalbidi12Port A
PA4Terminalbidi10Port A
PA5Terminalbidi9Port A
PA6Terminalbidi8Port A
PA7Terminalbidi7Port A
PB0Terminalbidi27Port B
PB1Terminalbidi28Port B
PB2Terminalbidi29Port B
PB3Terminalbidi30Port B
PB4Terminalbidi31Port B
PB5Terminalbidi32Port B
PB6Terminalbidi33Port B
PB7Terminalbidi34Port B
Net status
  • No nets have been defined yet. None of the above terminals are connected to any nets in the schematic.
What key nets still need to be created/connected
  • Power rails: connect VCC and Ground to your board’s power system.
  • Z80 data bus: connect the 8-bit data bus to the CPU/system bus.
  • Z80 control lines: connect chip enable, I/O request, read, and clock to the Z80 control bus; include any required port/control selects.
  • Interrupt chain: connect interrupt output and daisy-chain in/out to your system’s interrupt chain.
  • Handshaking: connect ASTB/BSTB and ARDY/BRDY to your peripherals as required.
  • Port I/O: connect PA0–PA7 and PB0–PB7 to external devices.
Add PIO chip symbol
Define key Z80 nets
Check missing Z80 signals
65 days
Sign up to send

To get started, talk to Flux or create a New Document.

Documents

    Documents are markdown text files which describe project goals, capture details, or even simulation outputs.

    Assets

    Z8420 Symbol.svg

    Z8420 Symbol.svg

    Z8420 SymbolDefault
    step

    DIP-40_W15.24mm.step

    DIP-40_W15 Model3D Model
    kicad_mod

    DIP-40_W15.24mm.kicad_mod

    DIP-40_W15 FootprintFootprint

    Z8420

    Z8420 thumbnail
    Parallel I/O, DIP-40 Z80 PIO parallel DIPW15.24mm

    Properties

    Texas Instruments Inc.

    U

    zilog.com/appnotes_download.php?FromPage=DirectLink&dn=PS0180&ft=Product%20Specification%20(Data%20Sheet)%20%20&f=YUhSMGNEb3ZMM2QzZHk1NmFXeHZaeTVqYjIwdlpHOWpjeTk2T0RBdmNITXdNVGd3TG5Ca1pnPT0=

    Z8420

    DIP-40_W15.24mm

    Pricing & Availability

    See prices from popular manufacturers for your project.

    Controls