Text
USB connector D+ ─── pad 1 ─── continuous D+ trace ─── pad 6 ─── USB PHY D+
USB connector D− ─── pad 3 ─── continuous D− trace ─── pad 4 ─── USB PHY D−
                                      82400102
Local 5 V port rail ────────────── pin 5 (VDD)
                                      │
                              C1: 100 nF ceramic
                                      │
Ground plane ─────────────────── pin 2 (GND)

• C1 recommendation: use a 100 nF ceramic bypass capacitor between VDD and GND immediately beside the array; select X7R or X5R and a voltage rating with margin above the rail and credible transients. This is an engineering recommendation, not a verified mandatory capacitor value from Würth. ST’s analogous rail-to-rail USB protection circuit shows a 100 nF VBUS bypass capacitor, and its guidance calls for short rail and ground connections.
• No TVS-specific pull-up, pull-down, enable resistor, or LED resistor is needed. USB termination and any series damping resistors remain requirements of the selected PHY; do not invent a resistor value based on the TVS array.
• Keep VDD on a valid, non-elevated rail during the required operating and fault states. Würth’s VDD-to-GND operating maximum is 6 V. If VDD can be absent while data is driven, assess rail injection and powered-off behavior; this research did not verify a Würth application instruction authorizing arbitrary floating-VDD operation.
• Protection of a high-current power input, prolonged overvoltage, or elevated USB-PD VBUS requires separately selected protection. This array is not a substitute for an overvoltage disconnect, fuse, or power-path controller.

• Place at the connector: put the array before long runs toward the PHY, minimizing the length of exposed connector-side traces. Connector-adjacent placement is a primary-source ESD-layout recommendation from TI; its general principle applies here, but its package-specific dimensions do not.
• Use symmetric flow-through routing: keep both data traces straight beneath the appropriate I/O pads, as Würth specifies. Engineering recommendation: preserve the interface’s controlled differential impedance, use comparable geometry for both channels, avoid long TVS stubs, and retain a continuous reference plane.
• Minimize return inductance, not just DC resistance: use a short, wide GND connection and a nearby via to the plane; TI explicitly recommends a large via or a wide trace to ground for ESD returns. Engineering recommendation: avoid a long neck or narrow thermal-relief spokes in the discharge path where the assembly process permits a direct connection. There is no verified universal trace-width number for this part; choose geometry from stackup, pulse path, and fabrication constraints rather than interpreting the pulse rating as DC load current.
• Place the rail bypass at the array: keep pin 5 → capacitor → pin 2/plane loop short. Short power and ground connections are important for comparable rail-to-rail protection networks. Thermal management is secondary to transient-path inductance in this application, but normal operation must still respect the component temperature range.
• Separate exposed and protected routing: avoid running connector-side traces alongside sensitive traces after the clamp, reducing coupled disturbances. TI’s ESD layout guidance addresses this separation. Validate signal integrity and ESD on the assembled product; a device rating alone is not system qualification.

1. Treating flow-through pads as separate signals or as a guaranteed internal series connection. Pins 1/6 share a channel designation and pins 3/4 share the other. Maintain the two continuous PCB nets beneath the pads; otherwise the routing can introduce an open circuit, an unwanted stub, or an incorrect third/fourth channel assumption.
2. Selecting protection from “5 V” alone. The channel clamp is 7.7 V typical at 5 A with an 8/20 µs pulse, while the cited ESD clamp condition is 10 V typical. Check the PHY’s transient tolerance, board-induced overshoot, grounding, and temperature-dependent stress capability. Do not assume the pulse rating means continuous fault protection or that VDD can withstand negotiated high-voltage VBUS.

• Würth Elektronik, 82400102 WE-TVS TVS Diode – High Speed Series datasheet, revision 001.002, 2021-05-06. Manufacturer PDF. Revision/date validated from the packaging-page evidence.
• STMicroelectronics, USBLC6-2 Very low capacitance ESD protection datasheet. Manufacturer PDF. Used for verified electrical characteristics and analogous rail-to-rail bypass/layout guidance. The exact revision/date of the extracted artifact was not independently validated; do not infer it from historical mirror copies.
• Texas Instruments, TPDxEUSB30 2-, 4-Channel ESD Protection for Super-Speed USB 3.0 Interface. Manufacturer PDF; manufacturer product page identifies Rev. G, June 1, 2021. Used for alternative characteristics and general ESD layout guidance, not for Würth-specific package geometry.
• Texas Instruments, TPD2EUSB30DRTR ordering page. Manufacturer ordering information. Confirms the three-pin DRT package purchasing identity.
• DigiKey, Würth Elektronik 82400102 product and ordering listing. Distributor page. Primary source for the distributor’s CT/TR/Digi-Reel options and ordering quantities; distributor catalog electrical data was not used to override manufacturer ratings.