I’ll research the manufacturer’s datasheet, verify alternative parts and ordering details, and create a cited application guide in the project’s Files tab.
I verified the pinout and bypass-capacitor guidance, and distinguished the 5 A pulse-test condition from a continuous-current rating. The guide will also flag the datasheet’s differing contact-ESD statements and clearly separate functional alternatives from drop-in replacements.
STMicroelectronics USBLC6-4SC6 is a monolithic, low-capacitance ESD protection array with four data-line protection channels and an integrated VBUS protection path. Its standard application is protecting USB 2.0 interfaces operating up to 480 Mb/s against connector-borne electrostatic discharge while limiting capacitive loading on the data lines.
1. Quick Specifications
Rating categories matter: absolute ratings are stress limits, not recommended operating targets. Electrical characteristics below are specified at ambient temperature 25 °C unless stated otherwise; this passive protection array does not have a conventional regulator-like recommended supply-voltage t...
Created and checked the USBLC6-4SC6 Application and Usage Guide, covering all seven requested sections with citations and source links. It includes practical wiring and layout guidance, two functional alternatives, sourcing details, and explicit caveats for unverified drop-in compatibility and the differing contact-ESD statements.
STMicroelectronics USBLC6-4SC6 is a monolithic, low-capacitance ESD protection array with four data-line protection channels and an integrated VBUS protection path. Its standard application is protecting USB 2.0 interfaces operating up to 480 Mb/s against connector-borne electrostatic discharge while limiting capacitive loading on the data lines.
1. Quick Specifications
Rating categories matter: absolute ratings are stress limits, not recommended operating targets. Electrical characteristics below are specified at ambient temperature 25 °C unless stated otherwise; this passive protection array does not have a conventional regulator-like recommended supply-voltage table.
Table
Parameter
Value / conditions
Category
Standard application
USB 2.0, up to 480 Mb/s
Manufacturer-listed application.
Normal rail context
Nominal 5 V USB VBUS; leakage characterized at reverse voltage 5.25 V
Application context / characterization condition, not a 17 V operating rail.
Leakage current
10 nA typical, 150 nA maximum at VRM = 5.25 V
Electrical characteristic.
I/O-to-GND capacitance
3 pF typical, 4 pF maximum at VR = 1.65 V
Electrical characteristic.
I/O-to-I/O capacitance
1.85 pF typical, 2.7 pF maximum at VR = 1.65 V
Electrical characteristic.
Clamping voltage
12 V maximum at IPP = 1 A, 8/20 µs, any I/O to GND
Pulse-test characteristic.
Clamping voltage
17 V maximum at IPP = 5 A, 8/20 µs, any I/O to GND
Pulse-test characteristic; not a continuous 5 A current rating.
Absolute ratings; distinguish from the separate level-4 statement below.
Operating junction temperature
−40 to +125 °C
Table 1 absolute-ratings entry; not an independently specified ambient-temperature range.
Storage temperature
−55 to +150 °C
Absolute rating.
Package
SOT23-6L, surface mount; 0.95 mm typical lead pitch
Mechanical specification.
ESD qualification caveat: the front-page compliance statement specifies IEC 61000-4-2 level 4 at 15 kV air / 8 kV contact, while Table 1 lists 15 kV contact. Preserve those distinct statements rather than advertising an unconditional system-level 15 kV contact capability; obtain ST clarification if that higher contact level is a contractual requirement, and test the assembled product.
2. Pinout & Connections
Pin assignments follow the manufacturer's Figure 1; verify package orientation against its drawing before footprint assignment. The example channel assignments below are design choices, not fixed USB polarity functions.
Table
Pin Number
Pin Name
Description
Best Practice
1
I/O1
Protected data-line connection
Connect to port A D+ at a short shunt tap along the connector-to-PHY route.
2
GND
Common protection return
Tie directly to the ground plane using a short, low-inductance path.
3
I/O2
Protected data-line connection
Connect to port A D−; maintain routing symmetry with D+.
4
I/O3
Protected data-line connection
Connect to port B D− for a two-port example, or another suitable exposed signal.
5
VBUS
Positive protection reference / protected bus connection
Connect to the protected nominal 5 V VBUS rail; put the local bypass capacitor close to pins 5 and 2.
6
I/O4
Protected data-line connection
Connect to port B D+ for a two-port example, or another suitable exposed signal.
The short I/O, VBUS, and ground connections are manufacturer guidance, not merely cosmetic layout preferences.
3. Standard Application Circuit
USB 2.0 data-line and VBUS ESD protection
Route each connector data signal to its USB PHY and connect one protection I/O pin to that same net. The array is a shunt protection device, not a series data switch: do not assume pins 1 and 6, or pins 3 and 4, are internally connected feed-through ends of one signal. The manufacturer specifies four data-line protection channels.
Connect pin 2 to board ground and pin 5 to the USB VBUS rail used as the positive protection reference; keep those paths short.
Fit a 100 nF ceramic bypass capacitor between pin 5 and GND, immediately beside the array. Section 2.3 / Figure 7 shows the 100 nF addition for optimized ESD protection; choose a capacitor voltage rating above the actual rail maximum and account for ceramic DC-bias derating.
Figure 14's USB application also shows 1 µF. Distinguish this application-level capacitance from the local 100 nF ESD-layout recommendation; include VBUS capacitance in the complete port's inrush and power design rather than adding unlimited bulk capacitance.
For one USB port, use two channels and leave the unused I/O channels unconnected; do not attach unused channels to unrelated rails. For a two-port implementation, the above table assigns four data nets. Sharing the array's VBUS reference is suitable only when both ports genuinely use a compatible common rail; do not short independently switched VBUS outputs together to share one protection device. These are schematic-integration recommendations derived from the common-reference topology, not an additional ST operating mode.
No pull-up, pull-down, enable resistor, or series current-limiting resistor is required to activate this protection array. USB PHY terminations and any series resistors belong to the PHY reference design, not to the TVS array. Connector shield bonding and USB-C CC termination are separate connector/system design tasks; this part has no shield or CC control pins and does not implement them.
Scope limitation: this is transient ESD protection, not a sustained-overvoltage disconnect, fuse, current limiter, or USB Power Delivery controller. Do not connect its VBUS reference directly to a higher-voltage negotiated PD rail without selecting protection expressly rated for that rail.
4. PCB Layout & Routing Guidelines
Place protection at the connector. Keep the exposed connector-to-array segment short, with the PHY on the protected side; ST identifies the connector as the usual disturbance source.
Minimize ground and VBUS inductance. Use short, broad copper connections and ground vias close to pin 2. Avoid long thin ground traces and restrictive thermal-relief spokes in the surge return; the objective is low pulse impedance, not a heatsink. ST explicitly requires short I/O, VBUS, and ground paths.
Preserve USB differential-pair geometry. Keep D+/D− reference planes continuous, minimize branch stubs, and maintain symmetric pad approaches. Determine trace width and spacing from the actual stackup and USB/PHY impedance requirement; the TVS datasheet does not provide a universal trace width. This is board-level signal-integrity guidance.
Place local bypass capacitance beside pins 5/2. The 100 nF capacitor should close a compact VBUS-to-ground loop, not sit remotely beside the power supply.
Keep load current out of the protection package. VBUS load current flows through PCB power copper, with pin 5 connected as a branch; size that copper for actual USB current, copper weight, and allowable temperature rise. Do not use the 5 A pulse-test condition to size a continuous-current path through the IC.
5. Common Pitfalls / Things to Watch Out For
Confusing pulse ratings with normal-operation limits. “17 V clamp at 5 A” does not permit continuous operation on a 17 V rail or continuous 5 A conduction. Likewise, the stated pulse clamp voltage does not prove a PHY survives every ESD event; waveform, overshoot, layout, and PHY tolerance must be evaluated together.
Using a two-channel feed-through assumption or a remote return path. This is a four-data-line array, not a part whose opposite pads are necessarily one signal. Confirm each pin's net, keep the VBUS/GND connections and bypass loop short, and do not rely on the device rating to compensate for a long inductive ground trace.
6. Popular Alternatives & Equivalents
These are verified functional alternatives, not blanket drop-in approvals. Compare operating voltage, capacitance at equivalent bias, clamp behavior at equivalent waveform/current, and required immunity before substitution.
Semtech; manufacturer lists four I/O lines, rail-clamp TVS protection, USB 2.0 power/data applications, and SOT-23 6L packaging. Manufacturer product page
Functionally similar; pin/footprint drop-in status not verified in this guide. Same package family alone is insufficient approval.
Check the current manufacturer pin diagram and land pattern. The Flux listing was found, but its indexed package field says SOT-23-5 despite six terminals: inspect the actual footprint before use.
Texas Instruments; four-channel ESD array in 10-pin USON/DQA.
Functionally similar only; neither pin-compatible nor footprint-compatible.
Redesign schematic/PCB. Its pin table has data pins, GND, and N.C., but no VBUS pin; provide separate VBUS protection where required.
Unverified candidate excluded: onsemi SRV05-4MR6T1G was investigated, but its datasheet citation extraction remained pending after retry. No verified drop-in claim or numerical comparison is made for it here; this is a lookup limitation, not evidence that the manufacturer lacks the information.
7. Sourcing & Purchasing Guide
Table
Attribute
Details
Primary Distributors
Buy directly through ST eStore, or check ST's product-page distributor availability for franchised regional sources. An exact-part listing was verified at TME. An exact-part Mouser listing was found but automated access was denied; its stock/MOQ was not confirmed. Exact-part DigiKey, Arrow, and LCSC purchasing terms were not independently verified in this research.
Packaging Options
Manufacturer delivery is tape and reel; base quantity 3,000, marking UL46. TME permits single-unit multiples from the 3,000-piece manufacturer reel. Cut-tape/re-reel service depends on seller and order quantity; do not assume an extra ST suffix is required.
Standard MOQ
1 unit at the checked TME listing; 3,000 units is the manufacturer reel/base quantity, not a universal distributor minimum. ST eStore also displays a 1–9-unit pricing tier. Reconfirm all checkout terms before ordering.
Sourcing Advice
Specify the complete MPN USBLC6-4SC6, STMicroelectronics manufacturer, SOT23-6L package, and desired seller packaging. Do not silently substitute a similarly named two-line version or an automotive suffix. Use direct/franchised channels, request traceable lot/date codes for production, and avoid untraceable marketplace stock. The UL46 marking supports incoming inspection but is not proof of authenticity.
Sourcing research date: 6 October 2026. Listings and commercial terms can change; no inventory reservation, price guarantee, or blanket distributor-authorization claim is made.
Semtech SRV05-4 product page: manufacturer functional, package, and order-code information. The page lists a datasheet release date of 15-Dec-2018; the datasheet revision itself was not independently established here. Used only for functional-alternative classification.
Texas Instruments TPDxEUSB30 datasheet: manufacturer datasheet, with citation-backed package and pin-function evidence above. The TI product page labels its linked datasheet Rev G, dated 1-Jun-2021; rolling PDF and packaging addenda may have newer dates, so that page label is not asserted as the revision of every retrieved PDF page.
TME exact-part purchasing listing: USBLC6-4SC6, used for seller-specific MOQ and reel quantity, not as the controlling source of electrical ratings.
Manufacturer facts carry inline evidence citations or direct primary-source links; layout/integration recommendations are identified as such. No schematic, symbol, footprint, or component-property changes were made in preparing this guide.