Text
Connector TX+ ───────┬──────────────────── PHY / mux TX+
                    └── pin 1, IO1
Connector TX− ───────┬──────────────────── PHY / mux TX−
                    └── pin 2, IO2
Connector RX+ ───────┬──────────────────── PHY / mux RX+
                    └── pin 4, IO3
Connector RX− ───────┬──────────────────── PHY / mux RX−
                    └── pin 5, IO4

pins 3 and 8 ───────────────────────────── local GND plane

• Place the TVS array at the connector. TI recommends placing it as close as possible to the connector. Keep connector-to-clamp routes short and segregate exposed routes from downstream circuitry to reduce transient coupling.
• Make both ground paths low inductance. Pins 3 and 8 must connect to ground. Engineering recommendation: use nearby ground vias and short, broad copper connections; avoid long necks or narrow thermal-relief spokes in the ESD return. Choose dimensions from the actual stackup and assembly rules, not an arbitrary high-current trace-width figure.
• Preserve differential-pair geometry. Engineering recommendation: maintain the interface's controlled impedance, minimize skew and pad-induced discontinuities, avoid reference-plane splits, and include package/footprint parasitics in channel assessment. Do not force one generic impedance value onto both USB and HDMI implementations.
• Keep routes straight and minimize coupling. TI recommends straight protected traces, separation from other traces and avoidance of sharp corners using rounded routing where practical. Use the optional NC-pad routing only with explicit PCB continuity to the protected IO pad.
• Use TI's DQA land pattern; do not invent a thermal pad or bypass network. This passive device has no supply to decouple. Engineering recommendation: check the manufacturer's mechanical/land-pattern drawings against the library footprint and the assembler's fine-pitch solder-mask/stencil capabilities before release; this guide is not a footprint audit.

1. Treating breakdown voltage as an operating-voltage allowance. A minimum positive breakdown of 5.5 V does not make this a 5 V logic or VBUS protector: the recommended IO range remains −3.6 V to +3.6 V. Also, the typical TLP clamp voltage is not a guaranteed safe voltage for every receiver; verify protection against the actual PHY and assembled-board ESD tests.
2. Assuming “flow-through” means internally connected signal inputs and outputs. Pins 6, 7, 9 and 10 are NC, not internal output pins. Route continuous copper to the corresponding protected IO pin and verify the PCB netlist; a good-looking symbol or package does not establish continuity.

• Texas Instruments, TPD4E02B04 datasheet, SLVSD85B, original November 2015, revised July 2016: manufacturer PDF. Sections used: Description; Pin Configuration and Functions; Absolute Maximum Ratings; ESD Ratings; Recommended Operating Conditions; Electrical Characteristics; Application and Implementation; Power Supply Recommendations; Layout. Revision is verified from the queried source.
• Texas Instruments product page: TPD4E02B04.
• Texas Instruments ordering page: TPD4E02B04DQAR, used to independently verify package and reel quantity where the datasheet addendum extraction was inconclusive.
• Texas Instruments authorized-distributor policy: Authorized Distributors.
• STMicroelectronics: HSP051-4M10 manufacturer product page, used for functional relevance; manufacturer datasheet, detailed lookup pending and revision/date unverified.
• Nexperia: PESD4USB3B-TBS manufacturer product page, used for functional relevance; manufacturer datasheet, detailed lookup pending and revision/date unverified by the datasheet extraction.
• DigiKey: TPD4E02B04DQAR product listing, primary distributor source for carrier options and quantity breaks.