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TB0.1/UCA0STE/CD4/A4/P1.4
DVSS
PJ.4/XIN
TA1.0/UCB0SOMI/UCB0SCL/P1.7
PJ.1/TDI/TCLK/MCLK/CD7
PJ.0/TDO/TB0OUTH/SMCLK/CD6
UCB0CLK/P2.2
PJ.2/TMS/ACLK/CD8
VCORE
PJ.5/XOUT
TA0.0/UCB0SIMO/UCB0SDA/P1.6
AVSS
TB0.2/UCA0CLK/CD5/A5/P1.5
PJ.3/TCK/CD9
AVCC
TA1.1/TA0CLK/CDOUT/CD2/A2/P1.2
TB0CLK/UCA0TXD/UCA0SIMO/ACLK/P2.0
TEST/SBWTCK
TB0.0/UCA0RXD/UCA0SOMI/P2.1
TA0.1/DMAE0/RTCCLK/P1.0
TA1.2/UCB0STE/CD3/A3/P1.3
TA0.2/TA1CLK/CDOUT/P1.1
DVCC
~{RST}/NMI/SBWTDIO

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    Documents are markdown text files which describe project goals, capture details, or even simulation outputs.

    Assets

    Texas_RGE0024C_VQFN-24-1EP_4x4mm_P0.5mm_EP2.1x2.1mm.step

    Texas_RGE0024C_VQFN-24-1EP_4x4mm_P0.5mm_EP2.1x2.1mm.step

    Texas_RGE0024C_VQFN-24-1EP_4x4mm_P0 Model3D Model

    Texas_RGE0024C_VQFN-24-1EP_4x4mm_P0.5mm_EP2.1x2.1mm.kicad_mod

    Texas_RGE0024C_VQFN-24-1EP_4x4mm_P0 FootprintFootprint

    MSP430FR5722IRGE Symbol.svg

    MSP430FR5722IRGE SymbolDefault

    MSP430FR5722IRGE

    MSP430FR5722IRGE thumbnail
    8kB FRAM, 1kB SRAM, QFN-24 TI MSP430 16-bit mixed signal microcontroller TexasRGE0024C

    Properties

    Texas Instruments Inc.

    U

    ti.com/lit/ds/symlink/msp430fr5722.pdf

    MSP430FR5722IRGE

    Texas_RGE0024C_VQFN-24-1EP_4x4mm_P0.5mm_EP2.1x2.1mm

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