USB Multi-Rail LDO Design

flux

0:00

Work done
  • Built the multi-rail LDO schematic blocks and nets: J1 as 2-pin +5V input, U1 TLV70033, U2 TLV70018, and 1 uF input/output caps C1 - C6 wired to +5V_USB / rails / GND.
  • Labeled rails as +5V_USB, +3V3, +1V8, +1V1, and GND.
Success criteria review
  • ✅ Includes the 2-pin power connector, two TLV700xx regulators, and 1 uF input/output capacitors per regulator.
  • ✅ All required nets are labeled (+5V_USB, +3V3, +1V8, +1V1, GND).
  • ❌ Cannot place the required TLV70011 SOT-23-5 as U3: the library search for "TLV70011" returns only TLV7011 comparator variants, not the TLV70011 LDO.
Next steps I can finish this as soon as we have a valid TLV70011 LDO part in the library (or you provide a specific part UID/MPN that exists there). Want me to:
  • Use an approved alternative 1.1 V fixed SOT-23-5 LDO you choose, or
  • Keep the schematic as-is and wait until TLV70011 becomes available?
84 days
joshdopp

joshdopp

you you do the pcb layout and routing?
84 days

flux

1:26

Clarifying capabilities and actions.

Summarizing conversation guidelines.

Clarifying layout capabilities.

Checking if I can make the changes for you.

Accessing knowledge base.

Calling @action for PCB layout.

Short answer: I can’t directly place components or route traces for you in Flux. Component placement, starting/stopping Auto-Layout, and manual routing are human-only actions.
What I can do for you:
  • Prepare the PCB: add/replace parts, make net connections, sync schematic-to-PCB, and change the board size.
  • Verify: check footprints, net names, and run reviews. DRC runs continuously and is shown in the Review tab.
  • Guide: recommend layout rules, placement order, and routing strategy.
If you want, I can get the PCB ready (parts, nets, board size) so you can run Auto-Layout and finish routing.
Ask placement guidance
Set board outline
Find footprints
Review decoupling
Routing strategy check
84 days
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    Properties

    flowchart TD J1["2-pin USB 5V input connector"] -->|+5V_USB| VINBUS["+5V_USB net"] GND0["GND"] --> GNDNET["GND net"] VINBUS --> U1["TLV70033 LDO"] VINBUS --> U2["TLV70018 LDO"] VINBUS --> U3["TLV70011 LDO"] U1 --> V33["+3V3 rail"] U2 --> V18["+1V8 rail"] U3 --> V11["+1V1 rail"] VINBUS --> C1["1uF input cap U1"] VINBUS --> C3["1uF input cap U2"] VINBUS --> C5["1uF input cap U3"] V33 --> C2["1uF output cap U1"] V18 --> C4["1uF output cap U2"] V11 --> C6["1uF output cap U3"] C1 --> GNDNET C2 --> GNDNET C3 --> GNDNET C4 --> GNDNET C5 --> GNDNET C6 --> GNDNET

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