STM32U3C5JI Microcontroller Implementation
please create the footprint yourself
Worked for 1 min 30 sec
I created a KiCad footprint scaffold for STM32U3C5JIY6QTR_WLCSP72_SMPS_B0TG here: download the
.kicad_mod. It is a 72-ball, 0.40 mm-pitch WLCSP footprint scaffold using the documented 3.67 × 3.58 mm body; before production release, the pad diameter/mask/paste should still be checked against ST’s exact land-pattern recommendation.Inspect that footprint file and verify the ball map against the datasheet.
Thought for 2 mins 34 sec
I could verify the datasheet side: STM32U3C5JIY6QTR WLCSP72_SMPS is a 72-ball, 3.67 × 3.58 mm, B0TG WLCSP, with ball rows A–J and columns 1,3,5,7,9,11,13,15, not a simple 0.40 mm rectangular A1–J8 grid. The generated footprint file URL is no longer readable by the file tool, so I can’t honestly confirm its actual pad list; however, if it used the earlier “generic 72-ball 0.40 mm pitch scaffold” pattern, it is not yet verified for production and likely needs regeneration to match the datasheet’s odd-column ball names and non-square pitch data: eD = 0.40 mm, eE = 0.69 mm, D1 = 3.00 mm, E1 = 2.77 mm, ball Ø 0.23–0.28 mm.
Correct ball map
Show mismatches
Check mechanicals
Import corrected footprint
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Design Notes — STM32U3C5JI Audio MCU Block
Status
This project implements a minimal STM32U3C5JI audio MCU block scaffold in Flux with power, reset/boot, HSE, SWD, 5x PDM microphones, and an I3C breakout. The schematic is functionally connected around the available placeholder MCU symbol, and the PCB is set up as an 80 mm × 100 mm six-layer board with production-oriented component placement.
Important caveat — U1 is still a placeholder component
The exact STM32U3C5JIY6QTR Flux library part is not currently available in the project/library search results, and this session cannot create/import a new part directly from the PDF. U1 therefore remains the available STM32L476JGY3TR WLCSP-style placeholder symbol/footprint, but its properties have been updated with STM32U3C5JIY6QTR PDF-derived WLCSP72_SMPS ball-map, I3C alternate-function, and mechanical/package metadata.
Production must not proceed until the exact STM32U3C5JIY6QTR WLCSP72_SMPS part is created/imported and U1 is replaced. All package-specific ball mappings, dedicated SMPS balls, analog supply balls, HSE pins, debug pins, I3C-capable pins, and audio/PDM/HSP/ADF pins must be revalidated against the official ST datasheet and final CAD symbol/footprint.
PDF source extraction
Source file:
stm32u3c5ci.pdf, ST DS15096 Rev 2.Device/package identification
- Product family/part: STM32U3C5xx; target MPN: STM32U3C5JIY6QTR.
- Package for STM32U3C5JI: WLCSP72.
- WLCSP72 package body: 3.67 mm × 3.58 mm.
- WLCSP72_SMPS is a 72-ball package with dedicated SMPS-related balls.
Figure 12 — WLCSP72_SMPS ballout / ball map
Table
| Row | Balls |
|---|---|
| A | A1=VDD, A3=VDDUSB, A5=PC12, A7=PD2, A9=PB3, A11=PB7, A13=VSS, A15=VDD |
| B | B2=VSS, B4=PC10, B6=PC11, B8=PB4, B10=PB8, B12=PB9, B14=PC13, B16=VBAT |
| C | C1=PA11, C3=PA12, C5=PA13, C7=PA14, C9=PB5, C11=PH3-BOOT0, C13=PC15-OSC32_OUT, C15=PC14-OSC32_IN |
| D | D2=PA8, D4=PA9, D6=PA10, D8=PA15, D10=PB6, D12=PC1, D14=PH1-OSC_OUT, D16=PH0-OSC_IN |
| E | E1=PC7, E3=PC6, E5=PC8, E7=PC9, E9=PA1, E11=PC2, E13=PC3, E15=PC0 |
| F | F2=PB13, F4=PB14, F6=PE14, F8=PE13, F10=PA7, F12=PA4, F14=PA0, F16=NRST |
| G | G1=PB15, G3=PB10, G5=PB11, G7=PE10, G9=PB0, G11=PA5, G13=PA2, G15=VSSA |
| H | H2=VDD, H4=VSS, H6=VSSSMPS, H8=PE11, H10=PB2, H12=PA6, H14=PA3, H16=VDDA |
| J | J1=PB12, J3=VDD11, J5=VDDSMPS, J7=VLXSMPS, J9=PE12, J11=PB1, J13=VDD, J15=VSS |
Requested I3C alternate-function verification from Table 21 / AF tables
Table
| Pin | WLCSP72_SMPS ball | Verified I3C-related alternate functions |
|---|---|---|
| PC0 | E15 | I3C2_SCL, AF6 |
| PC1 | D12 | I3C1_SDA, AF5; I3C2_SDA, AF6 |
| PB10 | G3 | I3C2_SCL, AF3; I3C1_SCL, AF6 |
| PB12 | J1 | I3C1_SDA, AF3; I3C2_SDA, AF6 |
| PB13 | F2 | I3C1_SCL, AF3; I3C2_SCL, AF6 |
| PB14 | F4 | I3C2_SDA, AF6 |
Current design choice: the primary inter-MCU I3C bus is routed as I3C1 using PB10=SCL and PB12=SDA through R7/R8 series damping and R5/R6 pull-ups. PC0/PC1 and PB13/PB14 remain documented as verified alternate I3C2-capable options for the final exact symbol/footprint review.
WLCSP72 mechanical/package data
Section 6.5 / Table 129 provides the following WLCSP72 B0TG mechanical data:
Table
| Symbol | Millimeters |
|---|---|
| A max | 0.58 |
| A1 min | 0.14 |
| A2 typ | 0.38 |
| A3 typ | 0.025 |
| b min / typ / max | 0.23 / 0.25 / 0.28 |
| D | 3.67 BSC |
| D1 | 3.00 BSC |
| E | 3.58 BSC |
| E1 | 2.77 BSC |
| eD | 0.40 BSC |
| eE | 0.69 BSC |
| eS | 0.40 BSC |
| N | 72 |
| SD | 0.10 BSC |
| SE | 0.31 BSC |
| aaa | 0.02 |
| bbb | 0.06 |
| ccc | 0.03 |
| ddd | 0.015 |
Assumption/ambiguity: the PDF extraction found the WLCSP72 package mechanical data but did not find a dedicated WLCSP72 recommended PCB land-pattern table. The footprint must therefore be reviewed against ST package application notes or an official CAD model before fabrication.
U1 placeholder assumptions
- Target MPN: STM32U3C5JIY6QTR.
- Intended package: WLCSP72_SMPS / B0TG.
- Placeholder part currently used by the schematic: STM32L476JGY3TR-style WLCSP MCU symbol/footprint.
- I/O and main supply assumption: 3V3.
- VDDA is filtered from 3V3 through FB1 and locally decoupled.
- VBAT is tied to 3V3 because no backup-cell domain is implemented in this minimal block.
- VDDUSB is tied to 3V3 for the USB-capable domain, even though USB data is not implemented in this block.
- HSE assumption: PH0/PH1 placeholder pins represent OSC_IN/OSC_OUT.
- SWD assumption: PA13=SWDIO, PA14=SWCLK, PB3=SWO, NRST=debug reset.
- PDM placeholder mapping remains PA5=PDM_CLK, PA0..PA4=PDM_D0..PDM_D4 and requires final ADF/HSP validation against the complete alternate-function tables.
- I3C mapping has been corrected from the earlier PB6/PB7 placeholder assumption to PB10/PB12 for I3C1.
- SMPS scaffold assumption: VDDSMPS, VLXSMPS, and VDD11 are included as named functional nets, but the current placeholder U1 does not expose the exact STM32U3C5JI dedicated SMPS balls. Final exact-part swap must connect H6=VSSSMPS, J3=VDD11, J5=VDDSMPS, and J7=VLXSMPS.
Implemented schematic decisions
- Power rails: 3V3, GND, VDDA, VDDSMPS, VLXSMPS, VDD11.
- VDDA is filtered from 3V3 through FB1 (GZ1608D601TF) and locally decoupled by C5/C6.
- Internal SMPS network scaffold: VDDSMPS input capacitors C11/C12, VLXSMPS to L1, L1 to VDD11, and VDD11 output capacitors C9/C10. Final SMPS pins must be reconnected after exact U1 replacement.
- Boot/reset: BOOT0 has 10 kOhm pull-down and boot button to 3V3; NRST has 10 kOhm pull-up, 100 nF capacitor to GND, reset button to GND, and SWD header routing.
- SWD: SWDIO/SWCLK/SWO/NRST routed to J1; SWDIO has 10 kOhm pull-up and SWCLK has 10 kOhm pull-down.
- HSE: 8 MHz FOXSDLF/080-20 crystal Y1 connected between OSC_IN and OSC_OUT with C13/C14 currently set to 33 pF. Recalculate load capacitance before production using the exact crystal CL and measured/layout parasitics.
- PDM microphones: MIC1 and M1-M4 share PDM_CLK and use individual PDM_D0..PDM_D4 data nets. LR straps alternate low/high/low/high/low for channel identity assumptions, but final channel plan should be verified in firmware.
- I3C breakout: J2 provides 3V3, GND, I3C_SCL, and I3C_SDA. The library pin named 5V is intentionally wired to 3V3 and must be renamed/replaced before production. R5/R6 are 2.2 kOhm pull-ups, R7/R8 are 22 ohm series damping resistors, and TP1/TP2 are on the bus lines.
Current pin/net mapping summary
Table
| Function | Current placeholder U1 pin/net | Intended STM32U3C5JI WLCSP72_SMPS ball/function | External/support connection | Production validation required |
|---|---|---|---|---|
| Main supply | VDD/VDDIO2/VBAT/VDDUSB to 3V3 | VDD A1/A15/H2/J13, VDDUSB A3, VBAT B16 | C1-C4, C7-C8, C22-C24 | Confirm exact rail grouping and required caps |
| Analog supply | VDDA/VREF+ to VDDA | VDDA H16, VSSA G15 | FB1, C5, C6 | Confirm VREF+/VDDA treatment and filtering |
| Ground | VSS/VSSA to GND | VSS A13/B2/H4/J15, VSSA G15, VSSSMPS H6 | common ground | Confirm all WLCSP ground balls |
| SMPS input/output | VDDSMPS/VLXSMPS/VDD11 scaffold | VDDSMPS J5, VLXSMPS J7, VDD11 J3, VSSSMPS H6 | C11/C12, L1, C9/C10 | Rewire to exact dedicated balls after exact part import |
| Reset | NRST | F16 | R2, C15, SW1, J1 | Confirm NRST network recommendation |
| Boot | BOOT0 | C11 PH3-BOOT0 | R1, SW2 | Confirm BOOT0/option-byte behavior |
| SWDIO | PA13/SWDIO | C5 PA13 | J1 pin 02, R3 | Confirm debug AF/default state |
| SWCLK | PA14/SWCLK | C7 PA14 | J1 pin 01, R4 | Confirm debug AF/default state |
| SWO | PB3/SWO | A9 PB3 | J1 pin 06 | Confirm SWO availability |
| HSE | PH0/PH1 | D16 PH0-OSC_IN, D14 PH1-OSC_OUT | Y1, C13, C14 | Confirm HSE pins and cap values |
| PDM clock | PA5/PDM_CLK | G11 PA5 | MIC1/M1-M4 CLK | Confirm ADF/HSP/PDM clock-capable AF |
| PDM data 0 | PA0/PDM_D0 | F14 PA0 | MIC1 DOUT | Confirm audio capture AF |
| PDM data 1 | PA1/PDM_D1 | E9 PA1 | M1 DOUT | Confirm audio capture AF |
| PDM data 2 | PA2/PDM_D2 | G13 PA2 | M2 DOUT | Confirm audio capture AF |
| PDM data 3 | PA3/PDM_D3 | H14 PA3 | M3 DOUT | Confirm audio capture AF |
| PDM data 4 | PA4/PDM_D4 | F12 PA4 | M4 DOUT | Confirm audio capture AF |
| I3C SCL primary | PB10/I3C_SCL_MCU | G3 PB10 = I3C1_SCL AF6 / I3C2_SCL AF3 | R7/R5/J2/TP1 | Confirm final selected I3C instance |
| I3C SDA primary | PB12/I3C_SDA_MCU | J1 PB12 = I3C1_SDA AF3 / I3C2_SDA AF6 | R8/R6/J2/TP2 | Confirm final selected I3C instance |
| I3C alternate | PC0/PC1, PB13/PB14 | PC0=I3C2_SCL, PC1=I3C1/2_SDA, PB13=I3C1/2_SCL, PB14=I3C2_SDA | currently not routed | Optional future bus/alternate routing |
Layout decisions
- Board outline is 80 mm × 100 mm with 2 mm corner radius.
- Stackup is Standard 6 Layer because the target MCU is a 0.40 mm pitch WLCSP and the design has multiple power domains plus clock/audio routing sensitivity.
- U1 layout currently has 72 pads, but the pad naming/geometry belongs to the placeholder STM32L476JGY3TR footprint, not the verified STM32U3C5JIY6QTR WLCSP72_SMPS B0TG footprint.
- Components are placed on the top side with U1 central, microphones along the top side, SWD/I3C headers near board edges, HSE and SMPS parts clustered around U1, and reset/boot controls accessible.
Validation results as of 2026-05-06
- U1 properties now include the extracted WLCSP72_SMPS ball map, mechanical data, and verified I3C alternate functions.
- Primary I3C schematic nets are now connected to PB10/PB12 rather than the earlier PB6/PB7 placeholder assumption.
- PB6/PB7 are intentionally marked no-connect in the placeholder symbol after the I3C move.
- Exact Flux library part search still did not find STM32U3C5JIY6QTR.
- Latest focused ERC review is clean for floating pins, missing power, and single-pin nets.
- Latest focused DRC review is clean for overlapping copper and missing footprints.
- Latest focused DRC review still reports 77 airwires because the PCB has not been physically routed.
- U1 layout currently exposes 72 pads, but it is still the placeholder footprint and must not be treated as a verified STM32U3C5JIY6QTR WLCSP72_SMPS land pattern.
Remaining production tasks
- Create/import the exact STM32U3C5JIY6QTR WLCSP72_SMPS part and replace U1.
- Revalidate all power, SMPS, HSE, SWD, I3C, and HSP/ADF/PDM pin mappings against the official STM32U3C5JIY6QTR WLCSP72 bond-out.
- Obtain or generate a verified WLCSP72 B0TG land pattern from ST CAD resources or an ST package application note; the PDF did not expose a dedicated WLCSP72 recommended land-pattern table.
- Rename or replace the I3C header symbol so its power pin is labeled 3V3 rather than 5V.
- Recalculate Y1/C13/C14 load capacitance from the selected crystal CL and PCB parasitics.
- Route the PCB and clear current airwires.
- Resolve any remaining overlapping-copper issues after exact U1 footprint replacement.
- Re-run final ERC/DRC/manufacturability checks after exact MCU swap and routing.
- Only after clean review, generate manufacturing outputs: Gerbers, BOM, pick-and-place, and assembly notes.
Status
Important caveat — U1 is still a placeholder component
PDF source extraction
Device/package identification
Figure 12 — WLCSP72_SMPS ballout / ball map
Requested I3C alternate-function verification from Table 21 / AF tables
WLCSP72 mechanical/package data
U1 placeholder assumptions
Implemented schematic decisions
Current pin/net mapping summary
Layout decisions
Validation results as of 2026-05-06
Remaining production tasks
