TMP127 Footprint Verification

flux

Verified jharwinbarrozo, UID d313fcfb-8800-40ba-b456-e02e11c2624f, URL /jharwinbarrozo/tmp127edbvrq1; latest version remains 3e31bda2-c6da-4e5b-ba37-c1dde201fa1e. No edits or publication: no confirmed electrical, mapping, overlap, or orientation fault; all change flags false.
  • Six terminals map 1:1 by identical terminal-element/pad UIDs: 1 active-low CS/Input, 2 GND/Ground, 3 SIO/Bi-Directional, 4 SCLK/Input, 5 NC/Not Connected, 6 VDD/Power In.
  • Global pad centers, mm: 1 (−1.30,+0.95), 2 (−1.30,0), 3 (−1.30,−0.95), 4 (+1.30,−0.95), 5 (+1.30,0), 6 (+1.30,+0.95). Rotated global rectangles are 1.00 × 0.70 mm; pitch 0.95 mm, row span 2.60 mm, outer copper span 3.60 mm, minimum edge gap 0.25 mm; distinct and nonoverlapping.
  • TI’s example lands are 1.10 × 0.60 mm, same pitch/span. Existing lands are therefore unqualified generator defaults, not an exact TI pattern; a difference from an example alone does not establish an unusable footprint.
  • Top view is 1–2–3 left, 6–5–4 right. Silk SVG pin-1 dot (−2.08854,−1.65 mm in SVG Y-down) converts to upper-left, consistent with pin 1; strokes 0.15 mm. Body is 1.60 × 2.90 mm. Intended parametric SOT-23-6 Model node exists, with computed height 1.175 mm versus TI maximum 1.45 mm; rendering omitted the footprint, not evidence of model absence.
  • Evidence: dsq_290385fd551ee34e6e0e ds1 ordering, ds2 pinout, ds3 body, ds4 maximum height; dsq_78c83b96cb886b875936 ds2/ds3 lands, ds4 pitch/span, ds5/ds6 orientation; ds3 expanded successfully.
  • Gaps: default lands lack solder-joint/process qualification; mask/paste, courtyard, full DRC, and actual rendered 3D fit were not qualified. Designator text is 0.70 mm versus applied profile minimum 0.80 mm, a manufacturing-profile concern rather than a confirmed part-definition fault. No production-ready claim.
J

jharwinbarrozo

flux

Focused confirmed land mismatch correction
Acceptance criterion is pads matching the verified manufacturer recommended/example pattern, not merely absence of proven unusability. Supplied dsq_78c83b96cb886b875936 ds2/ds3/ds4 are verified 1.10x.60 pads pitch.95 row2.6. Correct only pad sizes to that cited TI pattern, retain centers/mapping. Confirm nonoverlap/readback and publish corrected EXISTING part new version; return version and final measurements. No new review, no unrelated changes.

flux

I’ll set the six pads to TI’s 1.10 × 0.60 mm example pattern, retain their centers and mapping, then verify and publish the corrected part.

flux

Corrected only the six pad sizes and republished existing part d313fcfb-8800-40ba-b456-e02e11c2624f, owner jharwinbarrozo, at /jharwinbarrozo/tmp127edbvrq1; new version 6f3de443-e5cd-41da-95ea-b6a0692e2eeb.
Readback confirms global 1.10 × 0.60 mm pads, unchanged centers/mapping, 0.95 mm pitch, 2.60 mm row spacing, 3.70 mm outer copper span, and 0.35 mm minimum copper gap, with no overlap; evidence is dsq_78c83b96cb886b875936 ds2/ds3/ds4.
Change flags: pad sizes=true; all others=false; automated DRC returned no result, and prior process/3D qualification gaps remain—no production-ready claim.
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Files

Pins

Symbol

Layout

3D View

~{CS}
Pin Number
1
GND
Pin Number
2
SIO
Pin Number
3
SCLK
Pin Number
4
VDD
Pin Number
6
NC
Pin Number
5
Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
~{CS}
1
Input
Active-low chip select for SPI
GND
2
Ground
Ground
SIO
3
Bi-Directional
Peripheral serial input/output
SCLK
4
Input
Serial clock input
NC
5
Not Connected
No connect; leave floating or ground
VDD
6
Power In
Supply voltage

TMP127EDBVRQ1

TMP127EDBVRQ1 thumbnail