RT7310GE Verification


Verify RT7310GE only
Owner jharwinbarrozo UID3bc99b19-773d-446e-968b-dd5a9091c2f5 version89f5c55a-d8b7-4310-a732-2bbd39fad780. Datasheet https://pdf.digi-electronics.com/pdf/2158/RT7310GE-datasheet.pdf evidence dsq_36657e99d768fa14c89c ds2/3order Ggreen ESOT23-6 ds1pins:1GND Ground,2VDD Power In,3GD Output,4CS Input,5ZCD Input,6COMP Passive compensation. Two geometry queries dsq_2c8c540bdec8d729a0fd,dsq_a7c096271805f69ddd88 onlyoutline=>DEFAULT LANDS UNQUALIFIED. Bodywidth1.397-1.803length2.692-3.099height.889-1.295.
Check owner UID latestversion full~shortID URL,pins names/types/count/distinctmapping,actual copper sizeaxes/pitch/span/min gaps/no overlap,topview marker,parametric assetless model node/body/fit limits. Nominal not max envelope renderer omission not absence. Read-only preferred no clones/sharing/instances/unrelated edits. Publish corrected existing newversion only genuine repair. Compact pass/fail/unverified.
I’ll verify the published RT7310GE pin mapping, copper geometry, and nominal 3D model without changing the part.
RT7310GE: PASS for identity, pins, and nominal model; land qualification remains UNVERIFIED. No changes or republication made.
  • Identity PASS: owner jharwinbarrozo; UID 3bc99b19-773d-446e-968b-dd5a9091c2f5; latest/only version 89f5c55a-d8b7-4310-a732-2bbd39fad780; full project URL.
  • Pins PASS: six distinct terminal-to-pad mappings: 1 GND/Ground, 2 VDD/Power In, 3 GD/Output, 4 CS/Input, 5 ZCD/Input, 6 COMP/Passive; top-view pin-1 marker is upper-left beside GND, not mirrored.
  • Copper geometry PASS, qualification UNVERIFIED: actual rotated copper is 1.00 mm X × 0.70 mm Y, 0.95 mm pitch, 2.60 mm row-center span, 3.60 × 2.60 mm overall copper envelope; minimum adjacent gap 0.25 mm and opposing-row gap 1.60 mm; no pad overlap. Default lands remain unqualified against a manufacturer land pattern.
  • Nominal model PASS / maximum-envelope fit UNVERIFIED: active, assetless parametric SOT-23-6 Model node, zero offset/rotation, unit scale; body 1.600 × 2.900 × 1.175 mm, within supplied body limits (1.397–1.803 × 2.692–3.099 × 0.889–1.295 mm). This is not a maximum-envelope model; renderer omission is not evidence of absence.

COMP
Pin Number
6
ZCD
Pin Number
5
CS
Pin Number
4
GND
Pin Number
1
GD
Pin Number
3
VDD
Pin Number
2
Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
GND
1
Ground
VDD
2
Power In
GD
3
Output
External power MOSFET gate driver
CS
4
Input
Current-sense input
ZCD
5
Input
Auxiliary winding zero-current detection
COMP
6
Passive
Internal transconductance amplifier compensation node

RT7310GE

RT7310GE thumbnail