• Project description updated to a clear summary of the 1 kHz tone detector using CD4046 PLL and logic-level MOSFET output.
• System architecture property added with mermaid diagram:

Diagram

• Major ICs placed: 74HC4046AD,653 (U3), FDG1024NZ (Q1)
• Gate driver and protection: ZXGD3009E6TA (U4), BAV99 (D5,D6), BZT52B5V6-TP (D7)
• Passives added and values set (0603 footprint): • Decoupling: C15, C17 = 100 nF • VCO timing: R3,R6 = 220 kΩ; C18 = 1 nF • Loop filter: R7 = 47 kΩ; C19 = 100 nF • Input conditioning: C20 = 100 nF; R8,R9 = 100 kΩ; anti-alias R10 = 10 kΩ; C21 = 4.7 nF • Gate drive/protection: R11 = 100 Ω; R12 = 100 kΩ; R13 = 0.1 Ω; snubber R14 = 10 Ω; C22 = 100 nF
• Connectors placed: four 2-pin headers (J1–J4) for input, supply, and load
• Nets fully wired per plan: • 5 V/GND to all ICs and rails • CD4046 VCO network and loop filter • AC-cap, bias, limiter, RC filter from input to SIG_IN • Lock-detect through U4 to Q1 gate with pull-down • MOSFET power stage: drain to 12 V/load, source to GND with snubber
• All resistor and capacitor values annotated; protection and trim elements included

• ✅ PLL VCO set for ~1 kHz ±3% with chosen R/C
• ✅ Input network limits to 0–5 V and biases at mid-rail
• ✅ Lock-detect filtered and buffered drives gate cleanly
• ✅ MOSFET gate drive and protection circuitry present
• ✅ Schematic fully annotated with values and tuning options