Third export, still no passives. The IPC-D-356 netlist names exactly 23
components: IC1-IC4, J1-J8, TP1-TP11. Zero R and zero C designators. The eleven
STEP/DIR/ENABLE nets still have only two pads each — a buffer input and a J1 pin
— where a pull-down would make three. The only small SMD pads in the paste layer
are eleven single unpaired 1.0x1.0mm lands, which are the test points.
The drill fixes did land: J1 is 1.0mm and all seven terminals are 1.5mm. So the
export pipeline works — the passives specifically are not reaching it.
You have now stated twice that R1-R11 and C1-C4 are in the live design while the
export contains neither. Please diagnose that gap rather than re-adding them:
are they placed but unconnected, on a schematic sheet that is not included in
the layout, filtered out of the export, or never instantiated at all?
You’re right—the repeated mismatch means the previous validation method was not proving what reached the package you downloaded. I’ll diagnose the current export path directly: generate a fresh IPC-D-356, inspect its literal contents and the live layout hierarchy, and identify whether the passives are excluded, uninstantiated, or represented in a record class your parser/export is omitting. I will report the cause before making changes or exporting again.
Stop — my mistake, not yours. My netlist parser only read 317 records and
ignored the 327 continuation records, which is where R1-R11 and C1-C4 are
recorded. Parsed correctly, the export is complete: all eleven pull-downs are on
their nets, all four decoupling caps are across 5V and GND, J1 is 1.0 mm, and
all seven terminals are 1.5 mm.
This section supersedes the 15-resistor count, 4/4/4/3 distribution, ENABLE resistor assignments, and 200 Ω loading notice in the historical report below. The correction was completed and verified on 2026-09-17.
Completed: Retained R9, 1 kΩ 0805, as the only resistor between shared ENABLE_IN / GPIO21 and GND.
Completed: Removed R10, R11, R12, R15, four stale ENABLE trace segments in two redundant groups, and their four orphan standalone silkscreen service labels.
Completed: Preserved the ten independent STEP/DIR pull-downs R1–R8, R13, R14, unchanged at 1 kΩ 0805. Final count is exactly 11 × 1 kΩ 0805 resistors.
Completed: Live ENABLE_IN readback contains exactly eight component pins: J1 GPIO21; IC3 inputs 2, 5, 9, 12; IC4 input 9; R9 P1; TP9. R9 P2 is GND. All five independent ENA output channels are preserved. IC4 spare input 12 remains directly grounded; no spare-channel resistor is fitted.
Completed: Preserved C1–C4 (four 100 nF ceramic 0805 capacitors), all remaining component positions, connector mapping, test pads, and the 120 × 80 mm two-layer board. No placement or geometry tool was called.
Completed: Copper cleanup left zero airwires and zero redundant trace groups on independent routing-state readback. Rerouting was unnecessary because working shared-net continuity survived the deletions.
Completed: Fresh full ERC/DRC error/warning review at 2026-09-17T07:22:35.781Z returned no fab-critical, floating/dangling/redundant-copper, overlap or electrical findings. The only residual findings are the same five Manufacturer Part Number metadata Errors for H1–H4 and J1; these remain assembly/procurement notices rather than copper-fabrication defects.
Unattempted, intentionally: Gerber export, per instruction. No failed items in this correction batch.
Shared ENABLE pull-down loading is now nominally 3.3 mA at 3.3 V, rather than 16.5 mA. The following original report is retained as a historical record; use this correction wherever its resistor information differs.
Historical report before ENABLE correction
Scope and result
The added explicit verification requirement was incorporated: all 15 individual signal pull-downs and all four decoupling capacitors were re-read from the live schematic, including their values, packages, and net memberships. No electrical mismatch was found. Valid existing five-axis schematic, footprints, placement, test pads, and external legends were preserved.
This continuation routed the board, adding 234 routing nodes. Auto-route converged in one attempt, reducing 65 airwires to zero. The board remains 120 × 80 mm, two copper layers. No Gerbers were exported.
C1–C4, P1=5V and P2=GND; each adjacent to corresponding VCC
Board size, placement and accessible test pads
Completed — preserved after fit review
120 × 80 mm; no need for 130 × 90 mm
Stale copper cleanup
Completed inspection; deletion unnecessary
Before routing: zero redundant groups; no floating/dangling-copper findings
Route all nets
Completed
Converged; independent final routing-state read: zero airwires and zero redundant traces
Fab-critical DRC/ERC verification
Completed within available checks
No copper, placement, keepout, out-of-bounds or electrical findings returned; five non-copper MPN metadata errors remain
Exact cross-view cap-distance reconciliation
Failed to fully reconcile inspection representations
Routed bottom-layer ties measure 2.310 mm; SVG pad coordinates give 2.991 mm. Both meet ≤5 mm; see measurement note
Manufacturing export
Unattempted, intentionally
User explicitly prohibited Gerber export
Exact GPIO, buffer, terminal, and test-pad mapping
Every test pad is on the 3.3 V input side, not the buffered driver output.
Table
Axis / signal
GPIO
Input net
Buffer input → output pins
Output net
Terminal pin
Pull-down
Test pad
A STEP
25
STEP_A_IN
IC1 2 → 3
PUL_A_PLUS
J4.1
R1
TP1
A DIR
26
DIR_A_IN
IC1 5 → 6
DIR_A_PLUS
J4.3
R2
TP2
B STEP
27
STEP_B_IN
IC1 9 → 8
PUL_B_PLUS
J3.1
R3
TP3
B DIR
32
DIR_B_IN
IC1 12 → 11
DIR_B_PLUS
J3.3
R4
TP4
C STEP
33
STEP_C_IN
IC2 2 → 3
PUL_C_PLUS
J5.1
R5
TP5
C DIR
18
DIR_C_IN
IC2 5 → 6
DIR_C_PLUS
J5.3
R6
TP6
D STEP
19
STEP_D_IN
IC2 9 → 8
PUL_D_PLUS
J6.1
R7
TP7
D DIR
23
DIR_D_IN
IC2 12 → 11
DIR_D_PLUS
J6.3
R8
TP8
E STEP / Yaw
14
STEP_E_IN
IC4 2 → 3
PUL_E_PLUS
J8.1
R13
TP10
E DIR / Yaw
13
DIR_E_IN
IC4 5 → 6
DIR_E_PLUS
J8.3
R14
TP11
B ENABLE
21
ENABLE_IN
IC3 2 → 3
ENA_B_PLUS
J3.5
R9
TP9 shared
A ENABLE
21
ENABLE_IN
IC3 5 → 6
ENA_A_PLUS
J4.5
R10
TP9 shared
C ENABLE
21
ENABLE_IN
IC3 9 → 8
ENA_C_PLUS
J5.5
R11
TP9 shared
D ENABLE
21
ENABLE_IN
IC3 12 → 11
ENA_D_PLUS
J6.5
R12
TP9 shared
E ENABLE
21
ENABLE_IN
IC4 9 → 8
ENA_E_PLUS
J8.5
R15
TP9 shared
GPIO16/17 and GPIO2/12/15 have no signal-net connection. GPIO0 is not exposed by this J1 part and is not used. J1 VIN is on 5V; both J1 GND pins are on GND.
Pull-down count and distribution
Exactly 15 resistor components, all 1 kΩ, SMD_0805_2012Metric, each P1 on the corresponding signal input net and P2 on GND:
IC1: R1, R2, R3, R4, pins 2/5/9/12.
IC2: R5, R6, R7, R8, pins 2/5/9/12.
IC3: R9, R10, R11, R12, pins 2/5/9/12.
IC4: R13, R14, R15, pins 2/5/9.
The five ENABLE pull-downs really are five separate physical resistors, not one resistor counted five times. They intentionally share ENABLE_IN and therefore appear electrically in parallel: equivalent 200 Ω, drawing nominally 16.5 mA from GPIO21 at 3.3 V. This is an important bring-up load to verify, not an accidental net merge.
Spare bias: IC4 pin 12 (4A) is tied directly to GND. There is no additional spare-channel bias resistor to count. IC4 pin 11 (4Y) is unused and must not be tied to another output. All OE pins 1/4/10/13 on IC1–IC4 are on GND.
Decoupler verification and measured distances
Exactly four capacitor components: C1–C4. All are 100 nF = 0.1 µF, ceramic, 0805, mounted on Bottom. C1/C2/C4 are specified 25 V; C3 is 50 V. Each P1 is directly on the corresponding IC pin 14 5V net, and each P2 is directly on the corresponding IC pin 7 GND net, with no intervening component. Ground uses the common copper fill rather than an isolated point-to-point ground net.
Coordinates below are in board millimeters. The last column is Euclidean center-to-center distance calculated from the pad coordinates returned by the 2D inspection, not component-body spacing.
Table
Capacitor / IC
Capacitor center
SVG P1 center
IC pin 14 center
SVG pad-to-pin distance
C1 / IC1
(1.33, 13.50)
(2.28, 13.50)
(0.38, 15.81)
2.991 mm
C2 / IC2
(1.33, -10.50)
(2.28, -10.50)
(0.38, -8.19)
2.991 mm
C3 / IC3
(27.33, 13.50)
(28.28, 13.50)
(26.38, 15.81)
2.991 mm
C4 / IC4
(27.33, -10.50)
(28.28, -10.50)
(26.38, -8.19)
2.991 mm
Formula: sqrt(1.90² + 2.31²) = 2.991 mm. Component-center-to-VCC distance is 2.498 mm for all four.
Inspection-representation caveat: Persisted bottom-side 5V routing instead contains four straight local capacitor-to-VCC ties of 2.310 mm each, with mirrored-X bottom coordinates: x=-0.38 for C1/C2 and x=-26.38 for C3/C4. The routed endpoint Y differences are 15.81−13.499997 and −8.19−(−10.500003), both 2.310003 mm. The 2D SVG's bottom-pad transform appears inconsistent with that routing representation. Accordingly, 2.991 mm is the conservative displayed-coordinate measurement; 2.310 mm is the persisted routed-tie measurement. Both satisfy the ≤5 mm requirement, but these should not be presented as a single unqualified cross-tool exact dimension.
C1–C4 ground pads are direct-connect pads to GND fill. No GND airwire or ground-return-loop finding was returned. DIP pin 7 lies diagonally opposite pin 14; the return is through the common fill, not a claimed ≤5 mm ground trace to pin 7. No extracted return-path inductance measurement was performed.
Terminal order and service access
All five six-position connectors use the same pin-number order:
PUL+ (STEP+)
PUL− → GND
DIR+
DIR− → GND
ENA+ (independent buffer output)
ENA− → GND
Axis assignment is J3=B, J4=A, J5=C, J6=D, J8=E/Yaw. Silkscreen identifies every axis and all six polarities. Bottom-edge and right-edge legends are physically reversed/rotated as appropriate to their connector orientation; the electrical pin-number order above is unchanged. The central legend explains PUL=STEP and TP9=GLOBAL ENA GPIO21.
J2 remains the two-position 5V/GND power terminal. J7 remains the separate three-position bench terminal with all three pins GND. There is no J11.
Placement retained
J3/J4 centers (-31,34)/(12,34): top edge, outward wire access.
J8 center (54,0): right edge, outward wire access.
Driver-terminal bodies are approximately 31.04 × 10.20 mm. Same-edge six-position terminal body gaps are 11.96 mm.
J4-to-J2 body gap is approximately 9.15 mm; J6-to-J7 is 6.55 mm.
IC1/IC2 centers (8,±12), IC3/IC4 centers (34,±12). Same-row DIP envelope gap is 6.80 mm; vertical row-envelope gap is approximately 13.73 mm.
Test pads are accessible on Top at 8 mm horizontal pitch: TP1–TP6 at y=23, x=-4/4/12/20/28/36; TP7–TP11 at y=-23, x=-4/4/12/20/28. Their 2 mm envelopes leave 6 mm between adjacent pad envelopes.
H1–H4 retained near board corners at (±55,±35).
Combined component bounds x=[-57.8,59.1], y=[-39.1,39.1] mm; all within the 120 × 80 mm outline.
The 2D fit and successful routing support retaining 120 × 80 mm rather than expanding to 130 × 90. No top-side part obstructs a terminal screw location or the outward wire-entry region. Socket and probe access were not compressed. This is a board-level serviceability assessment, not a physical test with a particular screwdriver, wire ferrule, socket brand, or enclosure.
J1 geometry preserved
J1 was not moved, replaced, or geometrically edited in this continuation. It remains the verified 2×15 footprint with 2.54 mm pitch, nominal 25.4 mm row spacing, and 35.56 mm first-to-last row length. The live 2D pad positions run from x=-50.02 to -14.46 mm, with rows at approximately y=11.93 and -13.47 mm, confirming those dimensions at the inspection's displayed precision. Existing imported coordinates contain sub-micron rounding; no corrective rescaling was applied. J1 is centered at (-33,0), rotated 270°, with the USB end left and no component blocking leftward cable access.
Final checks and residual notices
Pre-route feasibility check: board valid, no issues.
Pre-route stale copper: zero redundant groups, no floating/dangling findings.
Auto-route: converged, no unrouteable nets, 65→0 airwires.
Full error/warning review at 2026-09-17T07:09:37Z returned only the five MPN issues below. A subsequent targeted review returned no copper, airwire, floating/dangling/redundant, component overlap, out-of-board, keepout, pad-access, OE/power, driver-conflict, or floating-pin findings.
Residuals are not hidden or relabeled as a completely clean manufacturing package:
Tool severity Error — five Manufacturer Part Number metadata findings: H1/H2/H3/H4 and J1 lack MPNs. The mounting holes are geometric features; J1 is a custom module/socket footprint. These do not indicate a PCB copper fabrication defect, but procurement/assembly identification remains open before ordering an assembled board.
Measurement notice: Bottom-side pad-coordinate/routing representation discrepancy described above. Both measured interpretations meet the requested decoupler distance.
Electrical loading notice: Five requested ENABLE resistors give a 200 Ω equivalent load. Verify actual GPIO21 high level with all five resistors populated.
Existing metadata notice: Empty legacy nets IC3_SPARE_2_OUT/3_OUT/4_OUT and ENABLE_PLUS remain as labels without component connections. IC3's legacy role text still mentions spare outputs; the verified live netlist uses all four IC3 channels for ENA. They are not extra physical channels or copper.
Assembly/bring-up not performed: Check actual module seating, USB plug clearance, socket envelope, terminal tool access, and driver enable polarity before fabrication release. Automated board checks do not replace that physical validation.
This report establishes completion of the routing and live schematic-verification batch; it is not a claim that procurement, physical prototype validation, or fabrication release is complete.
Current correction — one shared ENABLE pull-down
Historical report before ENABLE correction
Scope and result
Exact GPIO, buffer, terminal, and test-pad mapping