I’ll research the SX1262IMLTRT’s datasheet and official reference designs, then write a cited application guide covering wiring, layout, alternatives, and sourcing in the project files.
I found Semtech’s official resources and distributor packaging details, but the project’s datasheet lookup has not finished processing. I’m trying an alternate manufacturer PDF so the pinout and wiring recommendations can be verified.
I verified the ratings, all 24 pins plus the exposed pad, and the SPI and TCXO connections using a mirrored Semtech datasheet. I’m writing the guide now, with two non-drop-in alternatives and explicit flags for capacitor and RF-matching values that I could not verify.
The Semtech SX1262IMLTRT is a half-duplex sub-GHz RF transceiver supporting LoRa modulation, with a 150–960 MHz synthesizer range and transmit operation up to +22 dBm. It is commonly integrated with a host microcontroller in battery-powered LoRaWAN sensor nodes, smart meters, and proprietary long-range telemetry systems.
Scope: Practical SX1262 schematic integration, SPI control, clock selection, RF matching, PCB layout, and purchasing. This is not a verified production schematic or a universal RF BOM: band-dependent matching and unresolved supply-capacitor values must be checked against th...
Created and checked the SX1262IMLTRT Application and Usage Guide in the project files, covering all seven requested sections with citations and source links. It includes the complete pinout, integration guidance, and two clearly labeled non-drop-in alternatives.
Supply-capacitor and band-specific RF-matching values remain explicitly unverified; the next step is checking them against the selected Semtech reference-design BOM before schematic implementation.
The Semtech SX1262IMLTRT is a half-duplex sub-GHz RF transceiver supporting LoRa modulation, with a 150–960 MHz synthesizer range and transmit operation up to +22 dBm. It is commonly integrated with a host microcontroller in battery-powered LoRaWAN sensor nodes, smart meters, and proprietary long-range telemetry systems.
Scope: Practical SX1262 schematic integration, SPI control, clock selection, RF matching, PCB layout, and purchasing. This is not a verified production schematic or a universal RF BOM: band-dependent matching and unresolved supply-capacitor values must be checked against the selected Semtech reference-design package before release.
1. Quick Specifications
Absolute maximum ratings are stress limits, not permissible continuous operating conditions.
Table
Parameter
Classification
Value / conditions
VBAT and VBAT_IO supply voltage
Recommended operating range
1.8–3.7 V.
Practical shared supply
Engineering recommendation
Use a regulated 3.3 V rail with a host interface at the same logic voltage; verify burst droop rather than sizing solely from average current.
VBAT and VBAT_IO supply voltage
Absolute maximum
−0.5 to +3.9 V.
Temperature under bias
Operating range
−40 to +85 °C.
Temperature range Tmr
Absolute maximum
−55 to +125 °C; do not confuse this stress range with the operating range.
RF input level
Absolute maximum
+10 dBm; this is not a recommended receiver signal level.
Synthesizer range
Operating specification
150–960 MHz; the external RF network and antenna are band-specific.
TX current
Typical, not maximum
118 mA at +22 dBm, 868/915 MHz, with +22 dBm PA match; SX1262 core uses DC-DC and PA uses VBAT.
RX current
Typical, specific mode
4.2 mA for FSK 4.8 kb/s with DC-DC enabled; not a universal LoRa RX current.
Sleep current
Typical
160 nA cold start; 600 nA warm start with retained configuration.
24-terminal QFN, exposed ground pad, 4 × 4 mm, 0.5 mm pitch; height 0.90 mm nominal, 1.00 mm maximum.
2. Pinout & Connections
The manufacturer calls the exposed pad pin 0. Some EDA libraries number it 25; confirm pad mapping rather than assuming the library convention. All pin identities and descriptions below come from the datasheet pin table.
Best-practice instructions are engineering integration recommendations unless a separate citation is provided.
Table
Pin Number
Pin Name
Description
Best Practice
0 / EP
GND
Exposed ground pad
Solder to GND; provide a low-inductance ground and heat-spreading connection.
1
VDD_IN
Input to PA regulator
For SX1262 connect to VBAT, pin 10—not VREG as in SX1261.
2
GND
Ground
Tie directly to GND.
3
XTA
Crystal connection / reference input
Connect the crystal, or the TCXO output through the documented coupling network.
4
XTB
Crystal connection
Connect the other crystal terminal; leave open with the documented TCXO configuration.
5
GND
Ground
Tie directly to GND.
6
DIO3
Digital I/O / programmable TCXO supply
Reserve for TCXO supply if used; otherwise configure as the application requires.
7
VREG
Internal LDO/DC-DC regulated output
Connect the specified regulator capacitor; in DC-DC mode connect the inductor from DCC_SW. Do not drive with an external supply.
8
GND
Ground
Tie directly to GND.
9
DCC_SW
DC-DC switcher output
Use the DC-DC inductor path to VREG; keep the switching loop compact.
10
VBAT
RFIC supply
Connect regulated supply and local bypassing.
11
VBAT_IO
Digital-interface supply except DIO3
Match host logic voltage; do not apply 5 V logic directly.
12
DIO2
Digital I/O / RF-switch control
Connect to a compatible external RF-switch control circuit; enable RF-switch control in firmware.
13
DIO1
Digital I/O
Connect to an interrupt-capable host GPIO and map required radio IRQs.
14
BUSY
Busy output
Connect to a host input; wait for BUSY low before commands.
15
NRESET
Active-low reset input
Connect to host reset GPIO; avoid fighting the internal pull-up. A mandatory external 10 kΩ pull-up is not established.
16
MISO
SPI slave output
Connect to host MISO, not MOSI.
17
MOSI
SPI slave input
Connect to host MOSI.
18
SCK
SPI clock input
Connect to host clock; use SPI mode 0.
19
NSS
SPI slave-select input
Connect dedicated active-low chip select; keep high while idle. An optional host-board pull-up prevents floating during MCU reset; its value is a design choice.
20
GND
Ground
Tie directly to GND.
21
RFI_P
RF receiver input
Connect to the differential receive matching/balun network—not directly to a 50 Ω antenna.
22
RFI_N
RF receiver input
Connect to the other leg of the receive matching/balun network; do not ground it.
23
RFO
High-power transmitter output
Connect band-specific PA bias/matching/filter network and external RF switch.
24
VR_PA
Regulated PA supply
Preserve the reference-design PA supply, bypass, and RF bias network; not a general-purpose power rail.
3. Standard Application Circuit
MCU + SX1262 + external RF switch + single antenna
Use the official reference design for the exact frequency band and output power. Semtech explicitly labels its datasheet application schematics informational and directs designers to the latest reference designs.
1. Supply and internal regulators
Supply VBAT and VBAT_IO from compatible rails; a shared regulated rail simplifies logic interfacing. Connect VDD_IN to VBAT for SX1262.
Implement local capacitors on the external supply and internal regulator nodes exactly as in the selected official schematic. Place each capacitor close to its associated pin with a short ground return; use ceramic parts and account for DC-bias loss.
Unverified numeric details: The lookup did not reliably establish the VBAT, VBAT_IO, VREG, VDD_IN, and VR_PA capacitor values and voltage ratings. Do not substitute a generic “1 µF on every rail” recipe. Obtain the actual BOM and schematic from the reference-design download before fabrication.
For DC-DC operation, implement the 15 µH inductor and use a shielded, low-DCR part. Semtech specifies DCR ≤ 2 Ω, Idc ≥ 100 mA, and frequency ≥ 20 MHz in its selection criteria; inspect the current part datasheet rather than relying on the nominal inductance alone.
Size the upstream supply for radio TX bursts plus the host, TCXO, RF switch, and other loads; 118 mA is a typical operating point, not a guaranteed maximum current.
2. Precision clock
A crystal implementation uses the nominal 32 MHz reference at XTA/XTB; select the crystal and trim/loading arrangement from the current reference design, not a generic MCU oscillator circuit.
For the documented TCXO connection, connect output to XTA through a 220 Ω series resistor and 10 pF series DC-block capacitor; leave XTB unconnected.
DIO3 offers programmable 1.6–3.3 V TCXO supply. Keep VBAT 200 mV higher than the programmed TCXO voltage; a 3.3 V VBAT rail is therefore not appropriate for a 3.3 V DIO3 setting. Figure 4-2 shows 100 nF from DIO3 to GND.
Program the TCXO supply and startup delay to match the actual oscillator. Returning from TCXO mode to crystal operation requires complete reset.
3. Host control
Connect NSS, SCK, MOSI, MISO, BUSY, NRESET, and DIO1. Use SPI mode 0, with clock no faster than 16 MHz; start at a lower speed during bring-up.
For reset, the datasheet gives a typical 100 µs NRESET-low pulse; release reset, then wait for BUSY to go low before issuing configuration commands. Do not treat the typical pulse as a separately verified minimum timing guarantee.
4. RF front end
Route RFO through its PA bias, impedance-matching, and harmonic-filter network into the TX port of an external RF switch. Route RFI_P/RFI_N through the differential receive balun/matching network into the switch RX port; connect the common port through the reference-design filtering/matching to the antenna connection. The receiver network converts a single-ended nominal 50 Ω switch interface to the differential LNA's optimum impedance—it is not a generic 100 Ω digital differential pair.
If using DIO2 switch control, enable SetDIO2AsRfSwitchCtrl(1); DIO2 is high during TX and low during RX and the documented non-TX states. Check the chosen switch truth table and implement any complementary control needed.
Band-specific values remain open: There is no single verified matching BOM for the full 150–960 MHz tuning range. Use the reference package for the target band and PA setting; confirm output power, harmonics, and antenna match on the assembled PCB.
4. PCB Layout & Routing Guidelines
Follow the RF reference stackup. Semtech's high-power E428V03A example uses four-layer FR-4: top components/critical RF, layer 2 RF ground, layer 3 control routing, and layer 4 solid ground. Do not assume a two-layer copy has equivalent RF or thermal behavior.
Ground and heat spreading: Solder the exposed ground pad and connect it with low-inductance ground vias and copper. Avoid narrow thermal-relief spokes that undermine RF return and heat spreading; determine stencil segmentation and via treatment with the assembler. Ground-pad identity is documented; exact via count and pattern were not verified here.
RF geometry: Preserve the short receiver differential geometry, RF component placement, and ground-via locations from the reference layout. Calculate antenna-side 50 Ω trace geometry from the actual fabricator stackup; do not assign USB-style differential impedance to RFI_P/RFI_N.
Power and decoupling: Place local capacitors immediately beside their pins and keep the DCC_SW/inductor/VREG loop away from the oscillator and RF inputs. Size supply copper for burst-current voltage drop and ground return; no universal trace width is defensible without copper thickness, length, and acceptable drop.
Clock thermal stability: Do not accidentally heat the crystal with PA copper. E428V03A uses a copper void around the crystal on all layers to reduce thermal frequency drift, while the TCXO E449V01A example omits that isolation. Preserve antenna/RF return continuity when implementing the clock-specific layout.
5. Common Pitfalls / Things to Watch Out For
Copying the SX1261 power path into an SX1262 design. VDD_IN must be supplied from VBAT in the SX1262 reference implementation, not the SX1261 VREG connection. Copying the wrong PA path compromises the intended high-power operation; do not copy an SX1261 RF BOM blindly either.
Ignoring BUSY or peripheral configuration. A host that issues commands while BUSY is high can fail to configure the radio reliably. Wiring DIO2 or DIO3 is not enough: configure the RF switch/TCXO function and honor oscillator startup and switch control.
6. Popular Alternatives & Equivalents
No cross-manufacturer pin-compatible or footprint-compatible drop-in replacement was verified. The following are verified functional alternatives, not BOM-only substitutions; both require hardware and firmware redesign. Similar LoRa capability does not establish equal RF performance, interface compatibility, or certification.
Functionally similar only; neither pin- nor footprint-compatible
MCU plus integrated sub-GHz LoRa radio, rather than a stand-alone SPI transceiver. Can consolidate the host/radio architecture; requires a new board, MCU firmware, and RF implementation. ST identifies the exact part as UFQFPN48, not SX1262 QFN24. Manufacturer source.
Functionally similar only; neither pin- nor footprint-compatible
LoRaWAN modem module with ASCII UART interface and integrated RF support circuitry; Microchip lists RM105 with LoRaWAN 1.0.2 Class A/C support. Consider for a regional 868 MHz LoRaWAN redesign, not a universal frequency/output-power replacement or a 915 MHz substitution. Manufacturer source.
Both alternatives were found in the Flux library. Their listings are navigation aids, not proof of pin, footprint, or distributor-metadata correctness; verify the part project against the manufacturer drawing before building.
Manufacturer SX1262IMLTRT: QFN, tape and reel. DigiKey lists tape and reel, cut tape, and Digi-Reel distributor services. DigiKey.
Standard MOQ
Manufacturer minimum order / full reel: 3,000 pieces. DigiKey offers a 1-piece cut-tape quantity break; distributor repackaging minimums are not the manufacturer's MOQ. Future lists minimum and order multiple of 3,000. DigiKey; Future.
Sourcing Advice
Prefer franchised, traceable distribution; confirm current authorization with Semtech before a production order. Avoid untraceable marketplace or remarked stock. Order the complete SX1262IMLTRT MPN and confirm QFN package and tape/reel or cut-tape service; distributor CT/TR/DKR suffixes are ordering-service identifiers, not alternate silicon. Do not substitute SX1261 or SX1268 on name similarity alone.
JLCPCB assembly consideration
For JLCPCB builds, confirm the exact MPN, current LCSC listing or consigned/global-source path, assembly eligibility, and RF passive availability before freezing the BOM. This guide did not verify a current SX1262 LCSC code or JLCPCB stock.
Availability / pricing
No live inventory, lead time, or price guarantee is made. Recheck the distributor quote at purchase; online quantities and price breaks change.
Semtech, AN1200.40, Reference Design Explanation, Rev. 1.1, May 2018. Mirrored manufacturer application note; official document index lists a July 2, 2019 release. Used for SX1262 power path, reference stackup, crystal isolation, and receiver matching principles. Current design files should take precedence over this older explanatory note.
STMicroelectronics, STM32WL55CC manufacturer product page and exact STM32WL55CCU6 ordering entry: official source. Used for the functional-alternative assessment; page revision not specified.
Microchip, RN2483 manufacturer product page, including RN2483A-I/RM105 firmware/ordering information: official source. Used for the functional-alternative assessment; page revision not specified.
DigiKey, SX1262IMLTRT product listing:source. Used for distributor packaging and cut-tape quantity breaks.
Future Electronics, SX1262IMLTRT product listing:source. Used for reel order minimum and multiple.
Research date: October 7, 2026. Remaining verification: supply/regulator capacitor BOM and ratings, exact band-specific RF passive BOM, selected switch truth table and clock startup specification, and current purchasing/assembly availability. These gaps are intentionally disclosed rather than filled with estimated datasheet values.
1. Quick Specifications
2. Pinout & Connections
3. Standard Application Circuit
MCU + SX1262 + external RF switch + single antenna