Text
ADC-compatible reference rail ── track end (proposed pin 3)
                                    /\/\  10 kΩ track
Analog GND ──────────────────── track end (proposed pin 1)
                                       ↑
                                   pin 2, wiper ── optional 1 kΩ ── ADC_IN
                                                                     │
                                                               optional 100 nF
                                                                     │
                                                                Analog GND

• Required additional passive components: none for a basic divider into a sufficiently high-impedance input. No pull-up, pull-down, power pin, or mandatory potentiometer decoupling capacitor is required.
• Recommended starting filter for a slow human-operated setpoint: 1 kΩ series resistance from wiper to ADC input and 100 nF ceramic from ADC input to analog GND, located at the ADC. These values are examples to validate against the selected ADC's acquisition time, input capacitance, leakage and protection requirements—not Bourns requirements.
• Calculated source impedance: for an ideal unloaded 10 kΩ track, the maximum Thevenin resistance is R/4 = 2.5 kΩ at midpoint; including ±20% total resistance, it can reach 3 kΩ. With the example 1 kΩ series resistor, the maximum nominal RC time constant is 350 µs, rising to 400 µs at the maximum total resistance. Near an end stop the time constant is about 100 µs. Allow adequate settling and validate sample timing against the MCU datasheet.
• Calculated transfer function: VOUT ≈ x × VREF for an ideal linear, unloaded divider, where x is normalized electrical travel. This is not a guaranteed angle-to-voltage accuracy specification; mechanical dead travel, track linearity, contact resistance and ADC loading require characterization.
• Prefer ratiometric measurement: excite the track from the same reference used by the ADC, where that reference can supply the divider load. A 5 V divider must not directly drive a non-5-V-tolerant 3.3 V ADC.
• Add buffering if ADC acquisition or an external load requires lower source impedance. A capacitor can reduce noise, but it does not eliminate DC loading error.

• Use the correct mechanical drawing: PTV09A-4 is the horizontal/rear-mount, bushingless variant. Check all signal-hole and board-lock locations, drill sizes, shaft direction and board-edge clearance against that drawing; pitch and hole-size numbers are deliberately not guessed here.
• Design for user-applied torque: retain both board-lock features, keep adequate laminate around their holes, and support the PCB/enclosure so the signal joints do not carry knob loads alone. Check the actual knob and shaft envelope; this version is not a threaded-bushing panel mount.
• Route the wiper as a sensitive analog node: keep it short, use a nearby analog-ground return, and avoid parallel runs next to switching nodes, PWM motor traces and clocks. Differential-pair routing and impedance matching are not applicable to this component.
• Place optional filtering at the receiving ADC: keep the capacitor-to-ground loop small. Reference-rail decoupling is determined by the reference source/MCU, not by an invented potentiometer requirement; keep heat-producing devices away from the control.
• Make through-hole joints solderable: use thermal relief on plane-connected signal pads where needed for assembly and check annular-ring/drill rules against the chosen fabricator. Normal signal traces suffice for the example sub-milliamp divider; no high-current trace-width recommendation is appropriate. Respect Bourns' 300 °C maximum / 3-second soldering condition.

1. Treating voltage rating as permission to ignore dissipation. The 20 VDC / 50 VAC ceiling and 50 mW track rating both apply. The 50 VAC full-track example exceeds the power rating; a small rheostat segment is not entitled to dissipate the whole-track rating. No verified maximum wiper-current number is supplied here.
2. Copying a generic three-pin footprint or loading the wiper. A footprint must include the correct retention geometry and viewpoint, and the two board locks must not be mistaken for resistor connections. An ADC with insufficient acquisition time or a low-impedance load can distort an otherwise correct divider; verify the terminal map, clockwise behavior, end stops and ADC settling on a sample. This is an analog potentiometer, not a switch requiring digital debouncing; analog filtering may still be appropriate.

• Bourns, “PTV09 Series – 9 mm Potentiometer,” manufacturer datasheet PDF. Revision marking 01/25 is verified. Used for ratings, ordering fields, wiper identification, assembly limits and the applicable dimensional drawing. Numeric PCB geometry and rotation-direction interpretation remain unverified in this guide.
• Bourns, PTV09 product page: official series information.
• Alps Alpine, RK09K1130A6S: official product page. No revision/date displayed in the retrieved product-page evidence. Used to verify functional alternative characteristics; the separate series PDF lookup remained pending and is not used as evidence for those claims.
• TT Electronics, Model P09x Series, “Panel Potentiometer”: manufacturer datasheet PDF and P0915N official product page. Document revision/date not verified. Used for alternative ordering-code interpretation.
• DigiKey, PTV09A-4020F-B103 exact-part listing: listing. Distributor source for exact-part linear taper, construction, tray packaging and one-unit ordering.
• OnlineComponents, PTV09A-4020F-B103 exact-part listing: listing. Distributor source for tray packaging and 100-unit pack/MOQ/increment.