USB Sensor Node

Worked for 1 min 58 sec

Board is now set to a 100 × 80 mm, 4-layer stackup with internal GND and power planes. I’m placing the functional blocks next, keeping switching power away from the low-level DDS/analog path.

Worked for 7 mins 40 sec

flux

Placement is complete: USB/power is grouped on the left/lower-left, DDS and low-level analog are central, and the output amplifier sits behind the right-edge BNC. I’m checking and tightening any remaining decoupling-placement issues now.

Worked for 15 mins 19 sec

Created a project doc

PCB Layout Review — Programmable Function Generator

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Board outline set to 100 mm × 80 mm with 2 mm rounded corners. Stackup set to 4 copper layers for USB, SPI, analog output, and multi-rail po...

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PCB layout placement is complete on a 100 × 80 mm, 4-layer board: USB/power is on the left, LT3471 power is lower-left, DDS/control/conditioning are central, and the THS3091/BNC output is on the right. I ran placement, DRC, and BOM checks; details are captured in PCB Layout Review.

Open items:

Board is not routed yet, so airwires are expected.
DRC still reports exposed-pad footprint copper overlap on U3, U6, and U10.
Generic resistors/capacitors/inductors still need final orderable MPNs for assembly.

Suggested next steps:

Repair or replace U3/U6/U10 exposed-pad footprints.
Assign real MPNs/packages to generic passives and inductors.
Route the PCB, then re-run full DRC.

Fix footprints and BOM

Fix footprint overlaps

Assign passive MPNs

Route the PCB

Run full checks

Files

Schematic

Layout

3D View

Design Notes — Function Generator Architecture

Architecture Rationale

The selected design uses a DDS plus digitally controlled analog output chain. This is a practical implementation for a compact programmable function generator from 1 Hz to 1 MHz, while keeping BOM complexity manageable.

Selected Main Parts

Table

Function	Selected Part	Reason
MCU/control	STM32G0B1CBT6	USB FS, SPI, timers, active SMD MCU
DDS sine/triangle	AD9833BRMZ	SPI DDS, 28-bit tuning, 25 MHz clock, sine/triangle output
DDS clock	DSC6151HI2B-025.0000T	25 MHz 3.3 V CMOS oscillator
Input protection	MP5016GQH-Z	2.7–15 V eFuse/current-limit switch with OVP clamp and UVLO
3.3 V rail	MCP1703A-330 SOT-89 variant	Fixed 3.3 V LDO, sufficient for digital/control rail
± rail generator	LT3471EDD#PBF	Dual boost/inverting regulator suitable for split analog rails
Waveform mux	ADG758CPZ	Low-voltage mux with >10 MHz bandwidth for low-level signal selection
Amplitude control	AD5290	±15 V capable SPI digital potentiometer for gain control
Output amplifier	THS3091DDAR	Active high-voltage current-feedback amplifier, very high slew rate, ±15 V operation
Output connector	50 Ω BNC jack	Standard function-generator output connector

Key Datasheet-Derived Constraints

AD9833 output is about 0.6 Vpp and must be filtered/level shifted/amplified.
AD9833 requires 100 nF + 10 µF on VDD, 100 nF on CAP/2.5V, and 10 nF on COMP.
DDS MCLK is 25 MHz max; a 1 MHz output has limited waveform sample density, so sine/triangle quality is not high-end AWG grade.
±10 V at 1 MHz needs at least 63 V/µs sine slew rate; THS3091 provides large margin.
THS3091 requires careful current-feedback layout and datasheet-compatible feedback resistor values.
LT3471 ±15 V values are adapted from the datasheet ±12 V reference circuit; final regulator stability should be simulated/reviewed after layout parasitics and load are finalized.

Power Budget Snapshot

3.3 V rail: estimated 70 mA typical, 150 mA design allowance.
±15 V rails: output-stage and load dependent; high-Z signal output target keeps current modest.
USB input target: <1 A for high-Z operation.
The schematic is not sized for 20 Vpp into 50 Ω; that would require roughly 100 mA peak output current and a much stricter thermal/power design.

Output Specification Notes

Amplitude target: 0 to ±10 V peak, centered at 0 V.
Default assumption: high-impedance load, recommended ≥1 kΩ.
BNC connector is 50 Ω mechanical/RF standard, but current amplitude calibration is not specified into 50 Ω.
Include output series resistance and protection so accidental shorts/backdrive are less destructive.

Open Engineering Items Before Layout Release

Confirm desired load specification: high-Z only vs calibrated 50 Ω source/termination behavior.
Confirm whether front-panel controls/display are needed or USB-only control is acceptable.
Add calibration procedure for amplitude flatness and zero offset.
Run ERC and analog/power review after schematic wiring.
For production-grade waveform quality, consider replacing AD9833 with a higher-performance DDS/DAC architecture.

Architecture Rationale
Selected Main Parts
Key Datasheet-Derived Constraints
Power Budget Snapshot
Output Specification Notes
Open Engineering Items Before Layout Release