USB Sensor Node

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Board is now set to a 100 × 80 mm, 4-layer stackup with internal GND and power planes. I’m placing the functional blocks next, keeping switching power away from the low-level DDS/analog path.

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Placement is complete: USB/power is grouped on the left/lower-left, DDS and low-level analog are central, and the output amplifier sits behind the right-edge BNC. I’m checking and tightening any remaining decoupling-placement issues now.
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PCB Layout Review — Programmable Function Generator

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Board outline set to 100 mm × 80 mm with 2 mm rounded corners. Stackup set to 4 copper layers for USB, SPI, analog output, and multi-rail po...

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PCB layout placement is complete on a 100 × 80 mm, 4-layer board: USB/power is on the left, LT3471 power is lower-left, DDS/control/conditioning are central, and the THS3091/BNC output is on the right. I ran placement, DRC, and BOM checks; details are captured in PCB Layout Review.
Open items:
  • Board is not routed yet, so airwires are expected.
  • DRC still reports exposed-pad footprint copper overlap on U3, U6, and U10.
  • Generic resistors/capacitors/inductors still need final orderable MPNs for assembly.
Suggested next steps:
  1. Repair or replace U3/U6/U10 exposed-pad footprints.
  2. Assign real MPNs/packages to generic passives and inductors.
  3. Route the PCB, then re-run full DRC.
Fix footprints and BOM
Fix footprint overlaps
Assign passive MPNs
Route the PCB
Run full checks
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Schematic

Layout

3D View

Board Bring-Up Plan — Programmable Function Generator
Prerequisites
  • Equipment: current-limited USB-C 5 V supply, DMM, oscilloscope ≥100 MHz, ST-LINK/SWD programmer, optional frequency counter.
  • Start with no external load on BNC output.
  • Treat the BNC output as user-accessible analog I/O; verify offset and amplitude before connecting other equipment.
1. Visual Inspection
  • Check USB-C J1, BNC J2, SWD J3 orientation and solder joints.
  • Verify polarized/thermal-pad IC orientation: U1 MP5016, U3 LT3471, U4 STM32, U8 THS3091, U10 ADA4898.
  • Inspect LT3471 switch-node areas around L1/L2/L3, D1/D2, C25 for shorts.
2. Power Rail Verification

Table

RailSourceExpectedFirst Power Current LimitMeasure AtPass Criteria
VBUS_RAWUSB-C J15 V100 mA first testJ1 VBUS / U1 VCC4.75–5.25 V
5V_PROTU1 MP50165 V protected100 mA first testU1 SOURCE / C2within 100 mV of VBUS_RAW, no thermal rise
3V3U2 LDO3.3 V150 mAU2 VO / C63.2–3.4 V
+15V_AU3 LT3471+15 V nominal300 mA after shorts checkedC23 / U8 VS++14.25 to +15.75 V
-15V_AU3 LT3471-15 V nominal300 mA after shorts checkedC24 / U8 VS--14.25 to -15.75 V
Procedure:
  1. With power off, measure resistance from 5V_PROT, 3V3, +15V_A, and -15V_A to GND.
  2. Apply USB-C 5 V with 100 mA current limit. Confirm VBUS_RAW and 5V_PROT.
  3. Raise current limit to 500 mA and confirm 3V3, +15V_A, and -15V_A.
  4. Check LT3471 ripple on +15V_A and -15V_A before enabling waveform output.
3. Critical Signal Verification

Table

SignalNetExpectedTest
DDS clockDDS_MCLK_25MHZ25 MHz CMOSProbe X1 OUT / U5 MCLK
ResetNRSTHigh after RC delayProbe U4 PF2-NRST
SPI clockSPI1_SCKBursts during configurationProbe PA5
DDS rawDDS_RAW~0.6 Vpp AD9833 outputProbe U5 VOUT
BNC outputBNC_OUTCentered near 0 V after calibrationProbe J2 signal
4. Programming and Debug

Table

InterfaceConnectorSignalsTool
SWDJ3SWDIO, SWCLK_BOOT0, NRST, 3V3, GNDST-LINK / STM32CubeProgrammer
USB deviceJ1USB_DM, USB_DPUSB CDC firmware after flashing
Procedure:
  1. Connect ST-LINK to J3.
  2. Verify target voltage 3.3 V and read STM32 device ID.
  3. Flash firmware starter image.
  4. Confirm USB enumeration if USB CDC is enabled.
5. Functional Validation

Table

TestSetupExpected
1 kHz sineSine mode, mid amplitude, BNC unloadedStable sine, centered after zero trim
1 MHz sineSine mode, high amplitude, BNC unloadedWaveform present; purity limited by AD9833/sample density
TriangleTriangle mode at 1 kHz and 100 kHzTriangle-like output; verify slew/linearity
Square dutySquare mode, 10%, 50%, 90% dutyDuty changes at BNC output
Amplitude controlSweep AD5290 codeMonotonic amplitude change
Offset trimSweep DAC zero codeOutput DC offset shifts predictably
Known Limits to Validate
  • Current schematic is calibrated for high-impedance loads, not 20 Vpp into 50 Ω.
  • AD9833 waveform quality near 1 MHz is utility-grade; verify if low THD/SFDR is required.
  • LT3471 ±15 V regulator stability and ripple must be checked on the actual PCB layout.
Pass/Fail Summary

Table

SectionResultNotes
Visual inspection[ ] Pass / [ ] Fail
Power rails[ ] Pass / [ ] Fail
Programming[ ] Pass / [ ] Fail
Waveform output[ ] Pass / [ ] Fail
Amplitude/duty control[ ] Pass / [ ] Fail

  • Prerequisites

  • 1. Visual Inspection

  • 2. Power Rail Verification

  • 3. Critical Signal Verification

  • 4. Programming and Debug

  • 5. Functional Validation

  • Known Limits to Validate

  • Pass/Fail Summary