USB Sensor Node
Worked for 15 mins 19 sec
Created a project doc
PCB Layout Review — Programmable Function Generator
Board outline set to 100 mm × 80 mm with 2 mm rounded corners. Stackup set to 4 copper layers for USB, SPI, analog output, and multi-rail po...
PCB layout placement is complete on a 100 × 80 mm, 4-layer board: USB/power is on the left, LT3471 power is lower-left, DDS/control/conditioning are central, and the THS3091/BNC output is on the right. I ran placement, DRC, and BOM checks; details are captured in PCB Layout Review.
Open items:
- Board is not routed yet, so airwires are expected.
- DRC still reports exposed-pad footprint copper overlap on U3, U6, and U10.
- Generic resistors/capacitors/inductors still need final orderable MPNs for assembly.
Suggested next steps:
- Repair or replace U3/U6/U10 exposed-pad footprints.
- Assign real MPNs/packages to generic passives and inductors.
- Route the PCB, then re-run full DRC.
Fix footprints and BOM
Fix footprint overlaps
Assign passive MPNs
Route the PCB
Run full checks
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Board Bring-Up Plan — Programmable Function Generator
Prerequisites
- Equipment: current-limited USB-C 5 V supply, DMM, oscilloscope ≥100 MHz, ST-LINK/SWD programmer, optional frequency counter.
- Start with no external load on BNC output.
- Treat the BNC output as user-accessible analog I/O; verify offset and amplitude before connecting other equipment.
1. Visual Inspection
- Check USB-C J1, BNC J2, SWD J3 orientation and solder joints.
- Verify polarized/thermal-pad IC orientation: U1 MP5016, U3 LT3471, U4 STM32, U8 THS3091, U10 ADA4898.
- Inspect LT3471 switch-node areas around L1/L2/L3, D1/D2, C25 for shorts.
2. Power Rail Verification
Table
| Rail | Source | Expected | First Power Current Limit | Measure At | Pass Criteria |
|---|---|---|---|---|---|
| VBUS_RAW | USB-C J1 | 5 V | 100 mA first test | J1 VBUS / U1 VCC | 4.75–5.25 V |
| 5V_PROT | U1 MP5016 | 5 V protected | 100 mA first test | U1 SOURCE / C2 | within 100 mV of VBUS_RAW, no thermal rise |
| 3V3 | U2 LDO | 3.3 V | 150 mA | U2 VO / C6 | 3.2–3.4 V |
| +15V_A | U3 LT3471 | +15 V nominal | 300 mA after shorts checked | C23 / U8 VS+ | +14.25 to +15.75 V |
| -15V_A | U3 LT3471 | -15 V nominal | 300 mA after shorts checked | C24 / U8 VS- | -14.25 to -15.75 V |
Procedure:
- With power off, measure resistance from 5V_PROT, 3V3, +15V_A, and -15V_A to GND.
- Apply USB-C 5 V with 100 mA current limit. Confirm VBUS_RAW and 5V_PROT.
- Raise current limit to 500 mA and confirm 3V3, +15V_A, and -15V_A.
- Check LT3471 ripple on +15V_A and -15V_A before enabling waveform output.
3. Critical Signal Verification
Table
| Signal | Net | Expected | Test |
|---|---|---|---|
| DDS clock | DDS_MCLK_25MHZ | 25 MHz CMOS | Probe X1 OUT / U5 MCLK |
| Reset | NRST | High after RC delay | Probe U4 PF2-NRST |
| SPI clock | SPI1_SCK | Bursts during configuration | Probe PA5 |
| DDS raw | DDS_RAW | ~0.6 Vpp AD9833 output | Probe U5 VOUT |
| BNC output | BNC_OUT | Centered near 0 V after calibration | Probe J2 signal |
4. Programming and Debug
Table
| Interface | Connector | Signals | Tool |
|---|---|---|---|
| SWD | J3 | SWDIO, SWCLK_BOOT0, NRST, 3V3, GND | ST-LINK / STM32CubeProgrammer |
| USB device | J1 | USB_DM, USB_DP | USB CDC firmware after flashing |
Procedure:
- Connect ST-LINK to J3.
- Verify target voltage 3.3 V and read STM32 device ID.
- Flash firmware starter image.
- Confirm USB enumeration if USB CDC is enabled.
5. Functional Validation
Table
| Test | Setup | Expected |
|---|---|---|
| 1 kHz sine | Sine mode, mid amplitude, BNC unloaded | Stable sine, centered after zero trim |
| 1 MHz sine | Sine mode, high amplitude, BNC unloaded | Waveform present; purity limited by AD9833/sample density |
| Triangle | Triangle mode at 1 kHz and 100 kHz | Triangle-like output; verify slew/linearity |
| Square duty | Square mode, 10%, 50%, 90% duty | Duty changes at BNC output |
| Amplitude control | Sweep AD5290 code | Monotonic amplitude change |
| Offset trim | Sweep DAC zero code | Output DC offset shifts predictably |
Known Limits to Validate
- Current schematic is calibrated for high-impedance loads, not 20 Vpp into 50 Ω.
- AD9833 waveform quality near 1 MHz is utility-grade; verify if low THD/SFDR is required.
- LT3471 ±15 V regulator stability and ripple must be checked on the actual PCB layout.
Pass/Fail Summary
Table
| Section | Result | Notes |
|---|---|---|
| Visual inspection | [ ] Pass / [ ] Fail | |
| Power rails | [ ] Pass / [ ] Fail | |
| Programming | [ ] Pass / [ ] Fail | |
| Waveform output | [ ] Pass / [ ] Fail | |
| Amplitude/duty control | [ ] Pass / [ ] Fail |
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signal Verification
4. Programming and Debug
5. Functional Validation
Known Limits to Validate
Pass/Fail Summary
